Sales of discrete graphics processors for consumer PCs were up both sequentially and year-over-year in the second quarter despite soaring prices caused by component shortages, according to a newly released report by Jon Peddie Research. Although PC CPU shipments dropped in Q2 2026 year-over-year amid seasonality and shortages, sales of standalone graphics processors for consumer computers were up 12.2% sequentially and 14.1% YoY, the best market dynamics in some time.

Sales of graphics processing units for consumer PCs — which include integrated and standalone GPUs for desktops and laptops — totaled 75.5 million in the second quarter of 2026, up 10.4% quarter-over-quarter and 1.1% year-over-year, primarily driven by notebooks. This happened as the consumer CPU market contracted by 1.1% YoY amid a massive sequential drop in desktop CPU shipments and a significant rise in mobile CPUs shipments. Desktop GPU shipments declined by 4% quarter-over-quarter, while notebook GPU shipments surged by 16.8%, JPR claims.

But despite declining desktop PC unit shipments and modest growth in notebooks, unit shipments of discrete GPUs increased by 12.2% sequentially and 14.1% year-over-year in Q2 2026, according to JPR data. Jon Peddie Research does not publish absolute numbers of standalone graphics processors shipped in the second quarter, but our estimate is that around 20 million discrete GPUs were sold by AMD, Intel, and Nvidia in Q2, based on attach rates and Nvidia's market share and dynamics.

The results indicate that demand for PCs with discrete graphics remained remarkably resilient despite soaring component prices and slowing demand for desktop PCs. However, JPR's shipment data does not reveal whether the increase was primarily driven by gamers buying graphics cards, stronger demand for gaming notebooks, or other factors.

"The second quarter is typically down compared to the previous quarter," said Dr. Jon Peddie, president of Jon Peddie Research. "This quarter, discrete GPUs increased by 12.2%, even while a global memory crisis sent component prices soaring, driven by a mix of supply-side positioning, artificial demand shocks, and localized market dynamics."

Jon Peddie Research has yet to publish its complete desktop AIB report, which is expected later this month and will include market shares for AMD, Intel, and Nvidia; yet it is safe to say that the latter has maintained its undisputed leadership.

As for the overall consumer PC GPU market, Intel retained its leadership with a 56% market share as it increased shipments of consumer CPUs in Q2 2026. Nvidia came second with 23%, which is not bad at all considering that it only ships discrete GPUs. AMD came third with 21% share, up significantly from 14% in the same quarter a year ago, as it managed to gain seven percentage points of the consumer GPU market YoY amid growing sales of its consumer CPUs.

Nvidia started its AI business with humble AI accelerators, then moved to AI servers, and later to rack-scale and data center-scale platforms. With its multi-faceted AI strategy in place, the company is now looking beyond hardware. On Thursday, Nvidia said it had agreed to acquire Hugging Face, one of the world's largest platforms for distributing and developing open AI models, for $12.93 billion. Hugging Face will retain its brand and remain open to models, frameworks, clouds, inference providers, and computing platforms.

Nvidia positions the deal as an expansion of its commitment to open-weight AI models and as a way to popularize the use of artificial intelligence in general by enabling different types of developers to use appropriate open models for their products. The move is strategically important for Nvidia as it commands the lion's share of the AI hardware market and wants demand for its hardware to grow. Yet, Nvidia promises not to force participants of the platform into its hardware ecosystem.

Hugging Face currently serves more than 18 million developers, researchers, and creators, who have uploaded over 3 million models, 500,000 datasets, and 1 million applications, according to Nvidia. Furthermore, more than 200,000 companies use the service to find, assess, modify, and deploy AI models. Nvidia claims this business model will remain intact after the acquisition: Hugging Face will continue to host open-source and open-weight models from different developers and support multiple clouds and accelerator architectures.

Meanwhile, Nvidia says that its infrastructure, engineering resources, and global presence can improve Hugging Face's platform reliability, safety, model evaluation, inference, and deployment capabilities, which means that it will increase the portion of Hugging Face that relies not only on its hardware but also on its resources and global presence.

It is noteworthy that Nvidia itself already has a considerable footprint on Hugging Face. The company claims to have published more than 500 models and 250 open datasets, making it one of the platform's largest contributors. Nvidia also develops some of its models, software libraries, and tools openly so that third-party developers can modify and build upon them.

Interestingly, the deal appears to have originated with Hugging Face's founder. Nvidia's Jensen Huang says Clément Delangue approached him while evaluating the company's next stage and concluded that Nvidia could provide an appropriate home for Hugging Face, its community, and its open-model ambitions. As it turns out, Nvidia agreed to buy Hugging Face and keep developing it. The Hugging Face team will join the Nvidia organization and continue working on the project.

Intel's upcoming Core Ultra 400-series 'Nova Lake-S' CPU platform promises to be the company's biggest desktop launch in years, with range-topping processor offering up to 52 cores and gaming processors featuring up to 288 MB of bLLC cache, at least according to the rumor mill. Intel is reportedly on track to start mass production of its Nova Lake-S CPUs in the fourth quarter of 2026, according to a slide published by @wxnod. However, only the 28-core version will launch in the first quarter of 2027, with the 52-core model arriving later in the year, as we covered out of this year's Computex.

When initial leaks and roadmap disclosures about Intel's Nova Lake-S surfaced across 2025, the projected production schedule placed mass production in Q4 2026, so the new slide confirms that plan. Meanwhile, the actual CPU roll-out will be somewhat different to what Intel is used to as the company only intends to release unlocked 28-core SKU (or SKUs) in Q1 2027 and push the release of flagship models allegedly using two compute tiles featuring up to 52 cores to sometimes later in 2027. Some rumors pointing to a timeframe between late May and September, 2027. Normally, Intel launches flagship and unlocked models first. However, reports suggest the 52-core model will fit in a different class above a typical flagship, primarily targeting the HEDT crowd.

The slide revealed by the blogger does not look like an official Intel roadmap or an Intel presentation slide. A more plausible explanation is that the slide comes from a motherboard maker's presentation (or one of Intel's OEM partners), which compiled information the manufacturer got from Intel, which means that while it is most likely accurate, it is not final.

Intel's Core Ultra 400-series 'Nova Lake-S' CPUs will reportedly use up to 16 all-new high-performance Coyote Cove cores with 16MB of L2 cache, up to 32 energy-efficient Arctic Wolf cores, and up to four low-power Arctic Wolf cores, according to various leaks and the slide published by @wxnod. Even though each pair of Coyote Cove cores will reportedly share a 2 MB L2 cache, which will inevitably affect single-thread performance, Intel has an ace up its sleeve in the form of bLLC (big Last Level Cache), which will apparently scale to 288 MB to offer unbeatable performance in memory bandwidth-hungry applications, if media reports are correct. bLCC is apparently Intel's plan to fight back against AMD's X3D CPUs, which top the charts among the best CPUs for gaming.

The highest-end Core Ultra 9 400-series processors are expected to pack up to 52 cores using two compute tiles, whereas Core Ultra 7 400-series models are projected to feature up to 44 cores using two compute tiles, though exact configurations are currently unknown. Meanwhile, CPUs with two compute chiplets will reportedly consume up to 474W of power and will require motherboards featuring three 12V EPS power plugs.

On the I/O side of matters Intel's Nova Lake processors will reportedly feature a dual-channel DDR5 memory subsystem supporting up to DDR5-8000 modules as well as provide up to 24 PCIe 5.0 lanes directly from the CPU, including 16 lanes for graphics that can be split into two x8 or four x4 connections, plus two x4 links for SSDs.

Intel's new Core Ultra 400-series 'Nova Lake-S' processors for desktops will require Intel's new 900-series chipsets as well as will use an LGA1954 socket, according to leaks. Intel reportedly intends to keep LGA1954 around for a longer time than it usually does with its sockets, ensuring an upgrade path for years to come. We've already seen Z990 motherboards sporting the LGA1954 socket in the flesh.

Speaking of years to come, the slide lists Razor Lake and Hammer Lake processors that will succeed Nova Lake-S sometime after the fourth quarter of 2027. The slide does not provide technical details about either family, and we can only wonder whether Razor Lake corresponds to Core Ultra 500-series and Hammer Lake belongs to the Core Ultra 600-series, or both will be a part of one CPU family.

Intel notified its employees last week that it would no longer title its top scientists, researchers, and developers as 'Fellows,' but will call them 'distinguished engineers,' a change that will not affect their compensation but which means a lot more than a simple formality. The new designation reflects the company's new 'standard of technical leadership' that combines deep expertise with strategic vision and 'measurable tactical progress,' reports OregonLive.

Under the new hierarchy, Fellows become Distinguished Engineers, while Senior Fellows become Senior Distinguished Engineers. Intel CTO Pushkar Ranade told employees that the move represents more than a simple renaming and establishes a new standard for technical leadership.

"The future of Intel will be determined by leaders who combine deep domain expertise with outstanding problem-solving ability, creative innovation with disciplined execution, and an expansive and strategic vision with measurable tactical progress," the Intel CTO reportedly wrote.

Interestingly, despite the fact that at least a dozen semiconductor companies — including AMD, ASML, Applied Materials, Arm, Broadcom, IBM, Nvidia, Micron, Texas Instruments, Qualcomm, and TSMC — have Fellows, Ranade told Intel employees that the new titles are more consistent with terminology used elsewhere in the technology industry. While Apple, Google, IBM, and Microsoft have Distinguished Engineers, at Google, IBM, and Microsoft, Fellows are above Distinguished Engineers.

Intel established the Fellow title in 1980 to recognize employees with a sustained record of exceptional technical accomplishments. The designation had deliberately academic roots because scientific societies and then engineering organizations have long used 'Fellow' for distinguished members, for example, the Fellow of the Royal Society (FRS) or IEEE Fellow. So, by the time semiconductor companies, such as IBM, TI, or Intel, were developing formal technical career ladders, Fellow already carried a very specific implication: an engineer recognized by their peers as one of the leading authorities in the field.

Across semiconductor companies, the Fellow rank typically carries compensation, resources, and influence equivalent to a vice president (VP) or senior vice president (SVP), so that top architects and device physicists can shape company strategy without moving into people management (yet, Fellows did not work alone for obvious reasons). It is unclear whether Distinguished Engineers will now have similar resources and influence as Intel's VPs and SVPs that report to the CEO. Furthermore, at Intel, the Fellow (or senior Fellow) title reflected Intel's position as a semiconductor research powerhouse as well as its emphasis on long-term technology development.

The most notable people to hold the Intel Fellow rank title include distinguished specialists in microprocessor architecture, process scaling, high-speed interconnects, and silicon physics, including Marcian 'Ted' Hoff (the inventor of the Intel 4004 processor), Justin Rattner (for his work on massively parallel supercomputers), Mark Bohr (for leading Intel process technology development and fundamental work on things like strained silicon, hafnium, high-K metal gate, FinFET, etc.), Yan Borodovsky (for leading development and adoption of optical lithography extensions, immersion 193nm ArF lithography, and multi-patterning, just to name a few), and Ajay Bhatt (for leading development of USB, AGP, and PCIe). Perhaps the most unexpected Intel Fellow is Boris Babayan, who is primarily known as the father of Soviet supercomputing and the creator of the Elbrus VLIW CPU architecture. He became an Intel Fellow focused on optimizing binary translation and advanced compilers in November 2004, months after joining Intel.

All in all, Fellows historically had a very specific organizational and status value at Intel, as in many cases they have been the key people to solve Intel's strategic and tactical technical challenges while not being in a formal management role. From now on, Intel wants its Distinguished Engineers to be accountable for business decisions and essentially become managers.

The biggest question about renaming Fellows to Distinguished Engineers is whether this is done in a bid to further flatten the organization (after all, Intel got rid of 250 VPs out of 450, according to Intel's CFO), or is it a deliberate move away from the old research lab model, where Fellow signified scientific stature and long-horizon research, toward engineers whose status depends on products, execution and measurable business impact. For now, we do not have any answers to this question.

Being the world's largest contract chipmaker has its advantages for TSMC when it comes to negotiations with suppliers, as it naturally buys far more than others. However, it also has its difficulties because its requirements are dramatically larger than those of other foundries, and when they grow further, it gets exceedingly hard to source what it needs. Especially when its requirements increase nearly 2X in less than a year.

TSMC has nearly doubled its projected requirements for semiconductor production equipment since the end of last year as the foundry expands manufacturing capacity to address surging demand from the AI sector, said Cliff Hou, TSMC's deputy co-chief operating officer, during a fireside chat at Semicon Taiwan, reports FocusTaiwan. The world's largest foundry admits that it cannot meet all demand from all customers, though it is trying to catch up, according to Bloomberg.

TSMC makes projections about the number of tools it needs to purchase over the following year as well as its spending. After making that assessment late last year, the company discovered that by the end of the first quarter, the requirement had increased to 1.5 times that projection, and by July it had climbed to 1.9 times the original estimate, which means that TSMC's equipment needs had almost doubled in about six months.

TSMC itself attributes its increased needs to the number of new fabs that it is building in Taiwan and the U.S., though it should be noted that in addition to brand-new fabs, the company is also upgrading existing ones, which also need new machinery.

Interestingly, tool count does not seem to be proportional to tool cost. While TSMC increased its 2026 capital expenditure (CapEx) budget significantly in the recent eight months, it increased nowhere near 90%. Back in January, it guided 2026 CapEx to be from $52 billion to $56 billion. By April, it moved its estimate towards the high end of the original guidance, but in July it officially increased it to the range between $60 billion and $64 billion, or by around 15% if we only consider midpoints.

How exactly TSMC makes assessments about the number of tools it needs to buy the following year is something that remains to be seen, but perhaps a more pressing question for the industry is how it plans to acquire that equipment considering shortages of wafer fab tools due to massive demand from virtually all chipmakers.

The goal of next-generation HBM5 memory specification is to double performance and increase power efficiency compared to HBM4E, Samsung announced at the 'Memory Executive Summit,' an event that precedes 'Semicon Taiwan 2026.' Considering that it is barely realistic to double the data transfer rate of HBM4E in just one generation, the comment made by Samsung may imply that HBM5 will double the number of interface pins to boost bandwidth.

The goal of HBM5, which is currently under development, is to double the performance and improve the performance per watt by 20% compared to the HBM4E generation, according to Choi Jang-seok, the head of the product planning team of the memory business department of Samsung Electronics DS division. Previously, Samsung announced that its HBM5 memory stacks will feature a heat path block (HPB), which will reduce thermal resistance by 20% and simplify cooling of HBM5 modules.

Doubling HBM5’s per-stack memory bandwidth would result in peak bandwidth of around 4 TB/s per stack already in 2028 – 2029. TSMC expects AI accelerators to get to 20 – 24 HBM5/HBM5E per package configurations by the end of the decade, which means that these systems-in-packages will get a whopping 80 TB/s – 96 TB of memory bandwidth just several years down the road.

Although both DRAM makers like Micron, Samsung, or SK hynix as well as developers of HBM controllers and PHYs like Cadence, Rambus, or Synopsys already offer HBM4/HBM4E controllers and interfaces rated for 16 GT/s data transfer rates, the official JEDEC transfer rate for HBM4E will be around 12 GT/s.

If Samsung expects HBM5 to deliver twice the bandwidth of HBM4E, the HBM5 specification must either double the per-pin data transfer rate from 12 GT/s to 24 GT/s, double the interface width from 2,048 to 4,096 bits, or combine a wider interface with a higher data transfer rate. Increasing HBM5 memory stack interface width to 4,096 bits has so far been envisioned by KAIST and Marvell; however, this is certainly not an even semi-official confirmation of the specification's target.

From a performance-per-watt perspective*, widening the interface is generally easier than doubling the per-pin signaling rate. Higher per-pin speeds require faster drivers, receivers, clocks, equalization, tighter timing margins, and a more sophisticated PHY since maintaining signaling integrity at speeds well beyond 20 GT/s is not easy. But while a wider HBM interface moves more bits in parallel at a lower speed per wire, going from 2,048 to 4,096 pins means twice as many TSV/I/O paths, drivers, receivers, bumps, more complicated routing, and extremely complicated base die. So while a 4,096 I/O at moderate speed is probably best for pJ/bit, the interface/package complexity gets so extreme that it may offset the gains. Furthermore, such a wide interface Perhaps a 3,072-bit interface combined with a moderate increase in data transfer rate would be a reasonable engineering compromise, though engineers involved in JEDEC’s decision-making process may think otherwise. In any case, for now, any discussion of HBM5 specifications remains speculative.

Nonetheless, the target to double the bandwidth of HBM4E (2 TB/s per stack) within one generation is clearly a very aggressive one.

*It should be noted that achieving a 20% higher energy efficiency can be achieved not only by increasing performance, but by improving DRAM process technology, optimizing base die, lowering TSV I/O voltages, architectural changes, or power management.

China's ability to produce lithography tools is comparable to that of market leader ASML sometime in 2004, an analyst with UBS wrote in a note to clients. The situation may change in the next two or five years when Chinese companies start producing immersion DUV lithography systems in mass quantities, and Chinese chipmakers begin to deploy them for production of actual chips. However, China's semiconductor industry will remain well behind Western industry. "They seem to be at a similar stage to ASML in 2004," wrote Francois-Xavier Bouvignies, an analyst with UBS, in a note for clients, reports Bloomberg.

For years, China's pursuit of semiconductor self-sufficiency stemmed from its ability to produce mainstream chips on trailing nodes using fairly advanced, though not the latest, tools from leading producers such as ASML, KLA, and Lam Research. In recent years, China found itself in a new reality in which it could no longer obtain the latest chipmaking tools and had to build them domestically. Although companies like ACM Research, AMEC, and Naura have developed world-class chemical wafer deposition, cleaning, etching, and oxidation/diffusion tools that are now mass-produced and used by Chinese chipmakers, none of the Chinese companies have managed to develop a competitive lithography machine that can be used to make chips on more or less modern nodes and initiate its mass production.

Photolithography is generally considered the most technologically complex and demanding individual process in advanced semiconductor manufacturing. Firstly, lithography systems themselves are extraordinarily complex and contain tens of thousands of individual components. Secondly, the required positional accuracy is extraordinary, as a modern lithography scanner needs excellent resolution, overlay, focus control, scanner-to-scanner matching, CD uniformity, and line edge roughness, just to name some of the requirements. Finally, a competitive litho system must guarantee predictable uptime, defect density, and performance. Perhaps the key thing here is that all of the required features must be achieved without compromises, as, for example, a machine with high resolution and ideal uniformity that can process one wafer per hour cannot be used for mass production.

Historically, over a dozen companies produced lithography tools. However, as they became more complex, only ASML, Canon, and Nikon survived, with ASML being the undisputed market leader and the only maker of EUV lithography scanners.

As China is essentially developing a parallel semiconductor ecosystem, there have been reports of multiple entities working on lithography systems, including Shanghai Micro Electronics Equipment (SMEE), AMIES (which seems to be a SMEE spin-off that includes Aishengna and Yuliangsheng units), SiCarrier (reportedly controlled by Huawei), and even Naura (which denies that it is developing litho tools). SMEE, which was established in 2002, is by far the most important established Chinese manufacturer of litho tools. Meanwhile, so far none of China-based makers of lithography have established mass production of immersion DUV scanners capable of producing chips at 45nm and below.

SMEE reportedly formally introduced its first immersion DUV lithography system called SSA/800-10W and capable of making chips on nodes down to 28nm back in 2023. However, there have been no evidence that SMEE has indeed started mass production of the SSA/800-10W and that it has been adopted by a single manufacturer for mass production of chips. While it is conceivable that not all chipmakers announce deployment of breakthrough tools, especially keeping in mind that Chinese vendors like SMEE have plenty of foreign suppliers, we would have seen at least some indirect evidence (starting from procurement/acceptance records as well as component orders all the way to job postings and scientific papers) that SMEE started shipments of the SSA/800-10W in 2023 – 2024 by now, assuming of course that there were any shipments.

Interestingly, but the reports about China-made immersion DUV scanners now mass-produced by Shanghai Aishengna Electronic Technology Group (a unit, or an affiliate of SMEE) re-emerged this July, again, without any evidence. This time around, the reports did not even mention targeted nodes or throughput capabilities. To make matters even more suspicious is the lack of reports about shipments of evaluation tools to chipmakers (like ASML does this with its High-NA EUV machines) as well as preliminary results of their process qualifications (like Intel does with ASML's High-NA EUV machines).

For a first-ever Chinese immersion scanner, it is reasonable to expect Chinese chipmakers to use it on engineering wafers, characterize it against ASML machines, develop recipes, identify drawbacks, and pass that information back to SMEE, something that should take about a year. Only once that first machine performs adequately does it make sense to order and qualify multiple SSA/800-10W units for mass production. In fact, such qualification will likely take another year for a single layer and more time for additional layers. To that end, an insertion of an all-new lithography scanner into an existing flow will take at least two years, but likely more. To that end, once SMEE (or its business units) and its customers figure out how the first Chinese immersion scanner should work, these scanners will still be far from mass deployment.

In any case, without any real indicators that Chinese makers of wafer fab tools can produce and ship immersion lithography scanners to customers, we can only state what the UBS analyst did: China's lithography industry is in a position where ASML was in the mid-2000s.

Nvidia and MediaTek this week announced a major expansion of their partnership under which Nvidia is investing $3.5 billion in convertible bonds issued by MediaTek, while the latter adopts NVLink Fusion platform for its custom AI accelerators, local AI systems, and automotive platforms. On the one hand, MediaTek's adoption of NVLink Fusion enables it to design accelerators for Nvidia's fully developed rack-scale platforms. On the other hand, Nvidia gets a slice of the growing market of custom AI accelerators.

Having become the world's largest supplier of AI accelerators, Nvidia does not have direct rivals of comparable size. However, in a world where custom AI accelerators are becoming more widespread as more companies see benefits in bespoke solutions, Nvidia must hedge against their rise and ensure that its addressable market expands even if it does not win every accelerator design. One of the ways to achieve this is to spread its NVLink Fusion platform beyond its own products and to popularize it among users of custom hardware. The deal with MediaTek is aimed at exactly that.

AWS, Google, Meta, Microsoft, and now OpenAI are developing their own AI accelerators partly to reduce dependence on expensive merchant GPUs. Nvidia cannot necessarily prevent this trend, so NVLink Fusion gives it another strategy: if customers replace some Nvidia GPUs with their own XPUs, Nvidia wants those XPUs connected using NVLink, paired with Nvidia CPUs where appropriate, and deployed within Nvidia networking and rack architectures. Under the new arrangement, customers can bring an XPU architecture to MediaTek, then MediaTek and Nvidia will supply much of the technology surrounding the actual compute engine.

MediaTek will use NVLink Fusion as the foundation for custom accelerators that can evolve alongside future Nvidia architectures. The platform includes the NVLink Fusion chiplet, which connects custom XPUs to Nvidia's NVLink scale-up fabric using electrical or photonic interconnects; NVLink-C2C, which provides high-bandwidth, energy-efficient links between XPUs, Nvidia Rosa CPUs, and other compatible processors; and Nvidia NVHBM, which enables customized memory configurations and reserves more silicon area for compute.

Using Nvidia's NVLink Fusion platform for custom AI accelerators enables potential MediaTek customers to concentrate on their differentiated compute architecture while Nvidia and MediaTek provide connectivity, memory architecture, packaging, manufacturing, and rack-level technologies. Essentially, MediaTek's customers will get a pre-developed rack-scale platform for their custom AI accelerators, something they cannot get elsewhere. Since Nvidia tends to supply AI infrastructure platforms, not just AI accelerators, the deal with MediaTek fits perfectly into its strategy.

It should be noted that while hyperscalers like AWS, Google, or Microsoft can develop their own rack-scale solutions for AI and other workloads, smaller companies barely have enough resources to develop the whole rack-scale machine using off-the-shelf components.

"MediaTek is one of the world's great semiconductor companies, with exceptional expertise in system-on-chip design, connectivity, leading performance and power efficiency," said Jensen Huang, founder and CEO of Nvidia. "Together, we are building platforms that bring Nvidia accelerated computing to new markets and give customers the freedom to create differentiated AI systems at enormous scale."

The companies are also expanding their work on local AI computing. MediaTek previously collaborated with Nvidia on the GB10 Grace Blackwell Superchip powering DGX Spark. The collaboration was considered positive, so Nvidia and MediaTek now plan to cooperate on multiple generations of RTX Spark and DGX Spark processors for client systems, AI developer supercomputers, and enterprise workstations.

Finally, Nvidia and MediaTek will continue their multi-generation automotive collaboration. MediaTek's Dimensity Auto platforms integrate Nvidia AI technologies and RTX graphics for intelligent vehicle cockpits and can operate alongside Nvidia Drive AGX. Future generations will continue to wed MediaTek's automotive SoC expertise with Nvidia's accelerated computing, AI, graphics, and software technologies to build more advanced software-defined and AI-powered vehicles.

China's DRAM champion ChangXin Memory Technologies (CXMT) has started risk production of HBM3E memory, The Information reports. Although CXMT remains a generation behind the big three memory manufacturers, which are mass producing HBM4, it goes without saying that reaching the HBM3E milestone highlights the company's rapid technological progress.

Specifications of CXMT's HBM3E products are unknown, though keeping in mind that we are dealing with risk production, specifications of actual HBM3E products from CXMT may differ from risk production samples. Meanwhile, general JEDEC specifications are well known: HBM3E modules feature a 1,024-bit-wide memory interface, supports data transfer rates up to 9.6 GT/s per pin, and can stack 8 or 12 memory devices. Depending on the exact speed bins, HBM3E can provide up to 1.228 TB/s of memory bandwidth.

Capacity of actual memory stacks depends on the number of DRAM dies used in that stack: HBM3E products can offer 24GB of capacity using an eight-die stack or 36GB using a 12-die stack when built with 24Gb DRAM devices.

Several Chinese developers of advanced processors are already evaluating CXMT's HBM3E with their processors, including Alibaba Group's T-Head and Cambricon Technologies, according to the report. If testing and qualification proceed as planned, these companies could begin using CXMT's HBM3E in commercial products as early as next year.

Since every HBM package requires multiple large DRAM dies, growing HBM output could consume considerable DRAM manufacturing capacity, which is when CXMT's aggressive capacity expansion will be useful.

CXMT's manufacturing of HBM3E is important for multiple reasons and arguably the HBM3E generation itself matters less than CXMT's ability to manufacture usable HBM at all.

Firstly, HBM is one of the critical components of modern AI accelerators, so if CXMT's HBM3E qualifies with processors from Cambricon, T-Head, and other Chinese designers, China becomes less dependent on Micron, Samsung, and SK hynix for building high-performance AI hardware.

Secondly, despite being a generation behind HBM4, HBM3E is still very capable memory and can provide several TB/s of bandwidth, sufficient for powerful AI accelerators. In fact, many Chinese developers of AI accelerators do not necessarily need HBM4/HBM4E to build useful AI systems.

Thirdly, HBM is substantially harder than making ordinary DRAM. CXMT needs not only competitive DRAM dies, but also high-yield stacking, through silicon vias (TSVs), very fine interconnects, thermal management, packaging, and testing. Reaching HBM3E risk production proves that China's memory ecosystem is advancing beyond simply manufacturing commodity DRAM.

Finally, there is also an important geopolitical angle. Export restrictions constrain China's access to advanced AI processors and HBM, so a combination of Chinese-designed accelerators, CXMT HBM3E, and advanced domestic packaging indicates that China becomes one step closer to semiconductor self-sufficiency.

ChangXin Memory Technologies (CXMT) has announced in a social media post that it has started mass production of LPDDR6 memory for a Xiaomi smartphone, Reuters reports. This is not entirely unexpected given the general LPDDR6 mass-production timeline, but the announcement is still surprising because two China-based companies are ahead of industry announcements. Yet, there are caveats.

LPDDR6 is perhaps the most substantial upgrade to the GDDR-class memory ever. Firstly, it uses PAM3 signaling, which encodes 3 bits of information across two symbols, compared with the NRZ signaling used by LPDDR5/LPDDR5X. Second, the data transfer rate increases to 43.2 GT/s. Third, the reduced I/O width from 32 bits to 24 bits requires rework at both the hardware and software levels.

Given the differences between LPDDR5 and LPDDR6, the most important factor here is not exactly LPDDR6 manufacturing, but a broader view.

On the one hand, CXMT reached mass production of LPDDR6 roughly at the same time as the established DRAM leaders, meaning it is on par with them, if not ahead. This marks a substantial change from earlier generations, when Chinese DRAM technology generally lagged considerably behind Samsung, SK hynix, and Micron.

On the other hand, reaching mass production does not necessarily mean that CXMT has achieved full technological or manufacturing parity with its larger rivals. The official announcement covers only one smartphone maker and one model, meaning CXMT's LPDD6 still has to pass validation for other handsets and other makers.

Still, the significance of CXMT's announcement is hard to understate. CXMT is no longer merely catching up by introducing a new memory generation years after its international competitors. With LPDDR6, CXMT is entering the market during the standard's initial commercialization, which means the technology gap between China's leading DRAM producer and the industry's established players has narrowed considerably.

Which brings us to the question of whether CXMT can maintain this pace. Developing a competitive LPDDR6 device is one thing, producing it at high yields and in sufficient volumes to supply major customers is another. For now, we are talking about a niche smartphone with memory operating at undisclosed performance.

If CXMT can mass-produce LPDDR6 for the whole market and manufacturers, we may well have seen the change of the industry leader. Yet, given one niche device, we certainly cannot say so for now.

China's leading DRAM producer ChangXin Memory Technologies (CXMT) has filed a lawsuit against the U.S. Department of Defense in an attempt to overturn its classification as a company linked to China's military, Reuters reports. CXMT claims that it has no connection to the Chinese People's Liberation Army, and argues that the Pentagon's decision lacks supporting evidence, violated due-process requirements, and has damaged both its business and reputation.

The Pentagon initially classified CXMT as a Chinese military company in January 2025, when Joe Biden was the president. The Trump administration subsequently maintained the designation when the Defense Department updated the list in June. CXMT says it spent more than a year supplying information to the Defense Department in an attempt to overturn the classification and remove itself from the list.

The company claims the DoD published a notice in February indicating that CXMT would be taken off the list but withdrew that notice later the same day without any explanation. In June, the Pentagon classified CXMT as 'directly affiliated with MIIT and indirectly affiliated with SASAC and MIIT.' MIIT is China's Ministry of Industry and Information Technology, whereas SASAC is the State-owned Assets Supervision and Administration Commission of the State Council, an organization that formally owns the government's stakes in non-financial state-owned enterprises.

While CXMT memory can certainly be found in systems used by the PLA or China's secret services, this does not automatically make CXMT a direct supplier to these entities and therefore does not prove that CXMT is a Chinese military company.

CXMT points out the Pentagon's original motivation to include the DRAM maker in its list was a remarkably weak-looking 'military grade' argument. According to the complaint, DoD's 2024 report said CXMT contributed to China's defense industrial base partly because its DRAM is dual-use and cited an advertisement describing CXMT products as 'military grade.' CXMT says that advertisement came from an unauthorized distributor, which later admitted the characterization was erroneous.

In addition, CXMT claims that its DRAM products conform to JEDEC commercial standards and lack the requirements imposed on Chinese military-grade semiconductor components involving areas such as temperature, packaging, testing, and military oversight. Also, it says that should its products be made in the U.S., they would be classified as for 'purely civilian uses' and that it 'does not hold any licenses to manufacture products for military use.'

Inclusion on the Pentagon's list of companies linked to the Chinese military can result in restrictions involving U.S. government contracts, something that CXMT barely seeks. But more importantly, it can affect a company's commercial relationships (as many companies do not want to be affiliated with companies linked to the Chinese military) and reputation. Indeed, CXMT claims that since January 2025 the designation has continuously hurt it commercially and reputationally, and that the lawsuit is intended to protect its business interests.

When you serve a barely regulated emerging market worth trillions of dollars, you have to gear up your presence in politics beyond what usual lobbying or government affairs can do. This is exactly what Nvidia is doing by establishing its employees' federal political action committee (PAC), which will fund politicians whose positions are favorable to Nvidia's interests, reports Bloomberg.

The Nvidia employees PAC — which was registered with the Federal Election Commission on Thursday — will receive voluntary contributions from eligible Nvidia employees, who can provide up to $5,000 per year. The PAC will be permitted to contribute to federal candidates from both parties as well as party committees that express positions which align well with Nvidia's own goals, particularly in the fields of AI regulations, export controls, education, infrastructure spending, and workforce policy, just to name a few.

Nvidia reportedly told employees eligible to participate that decisions Congress makes over the coming years could have substantial consequences for the AI industry and everyday use of the technology. The company also noted that policymakers have increasingly focused on its industry and that decisions made in Washington affect both Nvidia's business and its customers' ability to obtain and deploy its technologies.

Nvidia has already substantially expanded its political operation. The company has spent more than $2.5 million on federal lobbying this year, an increase compared with the same period last year, according to lobbying disclosures seen by Bloomberg. In June, Nvidia hired Bruce Andrews, who previously headed government affairs at Intel and served as deputy secretary at the U.S. Commerce Department in Obama's government, as chief external affairs officer. In addition, Nvidia has hired five external Washington lobbying and government-relations firms to advocate for the company on a range of issues, including AI and trade policy, among others. The company also donated $1 million to the Trump Vance Inaugural Committee in January 2025.

Nvidia needs a PAC because lobbying and campaign contributions serve different purposes. The company can spend corporate money to lobby lawmakers, but it generally cannot use corporate treasury funds to contribute directly to federal candidates. Meanwhile, a company-sponsored PAC has a legal mechanism to collect voluntary contributions from eligible employees and direct that money to candidates and party committees from either party.

Meanwhile, unlike individual campaign contributions, donations made by the PAC will be publicly disclosed and subject to spending limits that do not increase with inflation. Furthermore, corporate PACs face growing resistance from lawmakers, according to Bloomberg. More than 270 House and Senate candidates have pledged to reject corporate PAC contributions this election cycle, the highest number since End Citizens United began promoting the commitment in 2018, Bloomberg claims. However, it is unclear whether these 270 are serious major-party nominees or current members of Congress, or some of the thousands of declared congressional candidates.

Nvidia is hardly alone in increasing spending on its influence in Washington, as most high-tech companies, now joined by AI giants, tend to spend millions on government relations and lobbying. The establishment of the PAC just highlights Nvidia's growing dependence on policies set in Washington.

Nvidia on Friday denied a report by the Wall Street Journal claiming that the company had put some transactions under its recently introduced 'take or pay' AI Compute Partnership on hold, less than two months after unveiling the initiative in early July and days before detailing the effort in its earnings call. The transactions were reportedly paused as some partners were irritated with Nvidia's attempts to influence their operations and because it raised internal concerns about potential antitrust scrutiny.

"The new business model we introduced in July that opens up compute access to the fast-growing AI ecosystem is still in place and continues to evolve due to high demand," a spokesperson for Nvidia told Tom's Hardware.

The report itself does not establish that Nvidia has abandoned the AI Compute Partnership program under which the company committed to rent capacity of newly built AI data centers as well as their minimum revenue, but claims that it put some deals on hold. Meanwhile, Nvidia's denial indicates that the program continues to exist, but is evolving, which means changing.

Per the report, it looks like Nvidia attempted to control how its 'AI Compute Partners' rented their capacity. The company told some cloud providers participating in the program that they could lease its GPUs only to customers approved by Nvidia, according to the WSJ report. The company also preferred to spread available capacity across multiple smaller AI companies instead of allowing a single large customer to take most or all of it. Some cloud operators reportedly pushed back against these restrictions, arguing that they should retain control over which customers they serve. Perhaps, in turn, Nvidia put some of the deals on hold.

While Nvidia does not lend any money or directly finance AI data center buildouts (which essentially means circular financing), it provides demand commitments and guaranteed revenue levels, which perhaps raised internal concerns about potential antitrust scrutiny. As a result, Nvidia could be revising the terms of the deals it inks with partners.

$36 billion of commitments

Modern AI data centers cost billions of dollars that must be spent on the premises, infrastructure, and compute hardware well before an operator has secured enough customer contracts to finance the buildout. Meanwhile, banks or infrastructure investors want confidence that enough of the future facility capacity will actually be rented. Under the program, Nvidia intends to use its own demand commitment on a portion of the facility's capacity in exchange for a percentage of the facility's revenue if demand is strong. This makes financing AI data centers easier as from the lender's perspective, part of the project's revenue stream is effectively supported by Nvidia rather than depending entirely on the operator's ability to find customers.

"Nvidia provides a take-or-pay commitment on a portion of the facility's capacity, a minimum revenue guarantee that gives lenders the confidence to underwrite the project, and in exchange, we share in a portion of the NeoCloud's revenue earned above that floor," explained Colette Kress, chief financial officer of Nvidia, during the company's earnings call. "In this model, we get paid twice, once on the hardware sale, and again through the share of rental revenue, a highly recurring stream layered on top of a one-time equipment purchase."

While actual percentages and economic terms have not been disclosed, it should work pretty straightforwardly. Nvidia provides a take-or-pay commitment that it rents, say, 30% of the capacity of a newly built facility and a minimum revenue guarantee over a period of six years. If the demand is strong and the facility rents 80% of its capacity, well exceeding the minimum revenue guarantee, Nvidia does not need to absorb the guaranteed capacity, and because revenue exceeds the agreed floor, Nvidia receives a percentage of the excess revenue. If the demand is weak and the facility can only rent 20% of its capacity, running well below the guaranteed revenue level, Nvidia's take-or-pay obligation would require it to cover the difference between actual revenue and the contracted minimum according to the specific agreement. Alternatively, Nvidia could rent back unused compute capacity for its own needs and cover the difference between the actual and guaranteed revenue level.

While at least some participants were reportedly irritated with Nvidia's alleged control of tenants, the program has proven to be quite a success so far. As of late July, just weeks after formally announcing the program, Nvidia had committed $36 billion in these new agreements that run for six years.

"Our commitments, which are typically six years in duration, totaled $36 billion as of July 26, 2026," an Nvidia filing with the Securities and Exchange Commission reads.

Nvidia has not disclosed which portions of monetizable capacities it typically commits, so it is impossible to figure out the value of the hardware it intends to supply under the $36 billion commitments.

Intel's confidence in its 14A (1.4nm-class) fabrication process is rising as defect density drops. The company's own design teams are at work developing products that will use the technology, while external customers are now asking about 14A volumes Intel can get them, according to David Zinsner, chief financial officer of Intel, who spoke at Deustche Bank's 2026 Technology Conference. The CFO went as far as saying that 14A is Intel's best process since 22nm technology from the 2010's. But while the comment is optimistic, there is a caveat.

"When you look at the defect density, 14A is tracking better than the target curve we had for 14A," Zinsner said at Deutsche Bank's 2026 Technology Conference. "It is also doing better than any of the previous nodes in terms of how quickly we are bringing down the defects. In fact, we have not seen this performance since 22nm, which is arguably one of the best nodes Intel has ever put out."

Intel intends to begin risk production of its own products on 14A fabrication process in the second half of 2027 and then initiate its high-volume manufacturing in 2028, so 14A is two years away from mass production. So, what Intel's CFO said at the conference is that at this point in 14A's development, its defect reduction trajectory looks at least as healthy as the trajectory of the company's exceptionally successful 22nm process at a comparable point in its development (i.e., in 2010). There are a couple of catches with such phrasing, though. Firstly, the defect density on 14A now is not necessarily equivalent to a defect density on 22nm two years away from mass production. Secondly, due to advances of wafer processing and inspection equipment, what Intel counts as a defect now may not be the same thing as what it counted as a defect 16 years ago. Furthermore, defect density itself does not directly equal product yield.

Intel's 22nm was the company's first manufacturing process to rely on FinFET transistors and at the time was the most advanced process technology in the world; the rest of the industry moved to FinFET devices only with their 14nm and 16nm-class nodes in 2014 and 2015. By contrast, 14A will use second-generation gate-all-around (GAA) RibbonFET transistors, second-generation backside power delivery called PowerDirect, and will be able to use High-NA EUV lithography due to extremely complex patterning. Keeping all of that in mind, Intel's claim that 14A defect density reduction is progressing unusually well this far ahead of HVM is certainly good news.

Meanwhile, comparing 14A to 22nm's successors should be quite comforting for Intel as 14nm mass production was delayed by a year due to insufficient yield, the first-generation 10nm node was a failure, 20A was cancelled, 18A defect density was high even as it hit HVM milestone, while the company did not share almost any information about the progress of its Intel 4 and Intel 3 nodes.

There are good signs for 14A though: external customers are already developing products for this node, whereas the interest from external customers is now practical rather than theoretical.

"We are now seeing demand from our internal customers on 14A [and] they are actually probably the most cynical bunch out of anybody," Zinsner said. "The fact that they are now designing products on 14A was a good confidence boost for us as well. Then, engagements with customers externally, from a foundry perspective has significantly increased. Lip-Bu and the team are now meeting on weekly basis with customers. They are moving away from just looking at data to thinking about 'how much capacity can I get?' 'what does that supply look like?' So, we are now at a point where we have conviction around customers on 14A externally as well."

Intel initiated mass production of its 22nm-based Ivy Bridge processors in late 2011 and early 2012 and released them commercially in late April 2012. The product was highly successful (though overclockers did not like it because of inefficient thermal interface material between the die and integrated heatspreader), and 22nm fabrication technology served the company for many years, first for CPUs in 2012 through 2016, then for other products. Intel's 14A also promises to be a long-lasting node for Intel.

High-bandwidth memory (HBM) is one of the key components of AI systems that is not currently assembled in the U.S., but this is going to change in 2029, when SK hynix initiates packaging of HBM memory modules at its facility in Indiana. This week, the company held a groundbreaking ceremony for its HBM production base in America and intends to start construction of the plant shortly.

SK hynix's HBM production site in West Lafayette, Indiana, will specialize in advanced packaging, testing, and R&D of HBM. The facility is set to cost the company around $4 billion, which highlights its advanced technology capabilities as well as vast capacity. The DRAM maker expects to open the cleanroom by October 2028 and begin volume production of next-generation HBM in the second half of 2029, which is about a year later than originally envisioned. Once commercial operations kick off, SK hynix expects the Indiana site to employ around 1,000 people.

Despite being described as an HBM production base, the Indiana site will not manufacture the DRAM wafers, but will package HBM stacks using DRAM wafers produced in South Korea and base dies produced in South Korea, Taiwan, or the U.S. Nonetheless, SK hynix intends to market the resulting devices as its first U.S.-made next-generation HBM products. Meanwhile, as custom HBM-class memory gains traction in the second half of the decade, assembling such stacks close to American customers may be particularly important both for SK hynix and its clients, as it enables SK hynix to shrink the feedback loop significantly.

In addition to building the advanced packaging and testing plant, SK hynix will also establish an Advanced Packaging R&D Testbed next to the manufacturing lines. The facility will enable SK hynix to work with customers, universities, and commercial partners on future packaging technologies, build prototypes, and quickly validate their performance and manufacturability in an actual production environment. In the era of customized HBM, such a facility could become a significant competitive advantage for SK hynix.

SK hynix also signed a memorandum of understanding with Purdue University to jointly research system integration and advanced packaging technologies, including HBM.

"The United States is the epicenter of AI innovation, bringing together premier customers, top-tier R&D capabilities, and partners and Indiana fab will become a gateway to deliver first Made in USA HBM products," said Kwak Noh-Jung, CEO of SK hynix. "We will expand our investments and collaboration in the U.S., grow together, and become the most trusted partner in shaping the future of AI in America."

Nvidia expects sales of the Vera Rubin platform to account for around 20% of its data center revenue in the third quarter of its fiscal year 2027, which will make it the company's fastest-ramping data center product in history. As Nvidia projects its revenue to be around $108 billion in Q3 FY2027, sales of Vera Rubin hardware alone will total around $20 billion in just one quarter.

"We see Vera Rubin accounting for about 20% of data center revenue in Q3," said Colette Kress, chief financial officer at Nvidia, during the company's earnings conference call with financial analysts and investors. "Having already received purchase orders from every major hyperscaler, AI cloud, and system OEM, we expect Vera Rubin to mark the fastest product ramp in Nvidia's history."

Data center revenue has accounted for around 92% of Nvidia's quarterly sales in recent quarters, so as long as Nvidia meets its $108 billion earnings projection in Q3, its data center revenue will reach around $99.36 billion, meaning that sales of its Vera Rubin platform hardware will be around $19.872 billion.

Nvidia began to ramp up production of Vera Rubin components — that include Vera CPUs, Rubin GPUs, BlueField 4 DPUs, and other units — this spring and commenced first revenue shipments of actual VR200 NVL72 racks in August, with Microsoft being the first to deploy commercial systems (at least according to Satya Nadella).

Normally, companies ramp up production and sales of their data center platforms for several quarters. Ramping up a data center platform from effectively no production revenue in Q2 FY2027 to 20% of revenue ($20 billion in this case) in just one quarter is a record not only for Nvidia, but perhaps for the whole industry, given Nvidia's scale. However, there is a catch: actual unit shipments do not look truly breakthrough.

Exact volumes of Vera Rubin units that Nvidia plans to ship in the third quarter of its fiscal 2027 are unknown. However, if Nvidia ships only VR200 NVL72 rack-scale systems, depending on their actual price and configuration (estimated from $5 million to $7.8 million per unit), Nvidia will supply from roughly 2,550 to approximately 3,975 machines containing 91,700 – 143,100 Vera CPUs as well as 183,500 – 286,100 Rubin GPUs.

These numbers are, of course, very rough since the company will sell a boatload of MGX servers and even Vera CPUs and Rubin GPUs separately, meaning that actual unit shipment volumes of these key components will be higher. Nonetheless, we are still talking about hundreds of thousands, rather than millions, of CPUs and GPUs, which is not particularly many. Still, given the stellar prices of leading-edge AI hardware, even relatively limited volumes of these components can generate tens of billions of dollars in revenue.

Nvidia has agreed to acquire Hugging Face for $12.9 billion, according to The Information, citing a person familiar with the deal. If the report is accurate and Nvidia indeed buys Hugging Face, the purchase could strengthen Nvidia's open-model strategy, provide another route to sell AI hardware, and help defend its hardware business as Anthropic, Google, OpenAI, and other major hyperscalers develop their own accelerators.

Nvidia sells hundreds of billions worth of AI hardware every year. Although the ubiquity of its CUDA software stack and leading performance of its hardware are the primary reasons why Nvidia's AI platforms are sold like hot cakes, another important factor is that many AI models were trained on Nvidia hardware and are optimized to run on it. Therefore, the more models trained on Nvidia hardware, the more products the company is going to sell eventually.

Hugging Face is an AI development platform best known for the Hugging Face Hub, a GitHub-like repository where researchers and developers publish, discover, download, and collaborate on AI models, datasets, and applications. Hugging Face also develops widely used software such as the Transformers library and provides tools and cloud services for training, optimizing, and deploying models on different types of AI hardware.

In addition to hosting models, datasets, and applications, Hugging Face provides software that helps developers optimize and deploy AI models on different CPUs, GPUs, and AI accelerators, while its Inference Endpoints service lets customers run models on managed infrastructure hosted by AWS, Google Cloud, and Microsoft Azure.

To make things simple, Inference Endpoints allows customers to select the provider, region, hardware type, and instance. What is important here is that the hardware used by Amazon, Google, and Microsoft is not all Nvidia. Hugging Face currently offers, depending on the provider, AWS Inferentia, AMD Instinct, Google TPU, Intel CPUs, and Nvidia accelerators, among other configurations.

OpenAI models, datasets, popular applications, and abilities to optimize and deploy AI models on different hardware make Hugging Face strategically important to Nvidia. On the one hand, the company can make the platform exclusively rely on its hardware, though this may face a backlash from the community, so this is something unlikely to happen in the short term (even assuming Nvidia is indeed set to buy Hugging Face). On the other hand, Nvidia wants open models to remain competitive with proprietary offerings from companies like Anthropic and OpenAI that may eventually get optimized for proprietary non-Nvidia hardware. Nvidia has been building its own Nemotron open models and has committed tens of billions of dollars to the effort. Furthermore, as Hugging Face grows, so is adoption of AI hardware in general and Nvidia hardware in particular.

Hugging Face is growing rapidly, but its revenue remains modest compared with the purchase price, according to The Information. The 10-year-old company recently reached approximately $150 million in annualized revenue, compared with about $100 million several months earlier, which puts Nvidia's price at roughly 80 times forward revenue, something that clearly highlights the strategic nature of the acquisition. Negotiations reportedly began after Hugging Face received acquisition interest elsewhere.

CEO and co-founder Clem Delangue said in June that paying subscribers doubled during the first half of 2026 and recently said the company was close to profitability. Demand has benefited from improving Chinese open models from Z.ai, Moonshot, and DeepSeek.

If Nvidia proceeds with the takeover, the transaction will be a part of Nvidia's increasingly aggressive investments across the AI ecosystem that spans from hardware to models to software. Last week, Nvidia agreed to pay $6 billion to license development technology from open-model developer Poolside and offered jobs to more than 100 employees. Nvidia also acquired Groq, Enfabrica, Essential AI, Illumex, and Kumo AI, just to name some.

OpenAI made quite a splash back in June, when it unveiled its 'Jalapeño' AI accelerator and revealed that the chip reached tape-out in just nine months. At the Hot Chips conference, OpenAI disclosed more details about the architecture of its Jalapeño inference processor as well as shared its target and real-world performance numbers. The company claims its NUMA-style spatial architecture enables Jalapeño to outperform Nvidia's GB200 and GB300 in low-latency inference and in terms of performance-per-watt, while a 2,048-processor system scales to 27 exaFLOPS and 32 PB/s of aggregate memory bandwidth.

A massive chip with massive scaling

OpenAI's Jalapeño is a massive AI inference accelerator co-developed with Broadcom, with 216 GB of HBM4 memory and up to 15.4 TB/s of bandwidth. The processor delivers up to 3.4 MXFP8 PFLOPS as well as up to 13.4 MXFP4 PFLOPS at 700W, which makes it suitable for inference, though the MXFP4 format may not be enough for training. The ASIC has a 700W power rating and operates at 1.70 GHz on silicon already running in OpenAI's labs, though OpenAI's engineers said at Hot Chips that the plan is to increase clocks up to 1.80 GHz, perhaps to get higher peak performance.

On the scalability side of matters, Jalapeño can scale to 128 accelerators in a local rack interconnected using Ethernet at 600 GB/s and to 2,048 ASICs in a 16-rack pod configuration at 200 GB/s per processor. The complete system offers 27 EFLOPS of MXFP4 performance, 432 TB of HBM4 memory, and 32 PB/s of aggregate memory bandwidth. For connectivity, OpenAI uses Broadcom Tomahawk 6 Ethernet switches and what it calls a 'half-flattened' two-level Clos topology that provides higher bandwidth for tensor-parallel traffic, lower bandwidth for expert-parallel communication, and prioritizes low latency for both. During the Q&A session, OpenAI confirmed that the scale-up network uses Ethernet with 200-Gb/s links. Jalapeño's physical hardware around the Broadcom-made chip is set to be made by Celestica.

On paper, Jalapeño's specifications look good, but they barely look impressive compared to Nvidia's Blackwell Ultra accelerators (10 FP8 PFLOPS, 20/15 sparse/dense NVFP4 PFLOPS). However, OpenAI argues that raw compute and memory bandwidth are not what makes its Jalapeño platform different.

The company says a 128-ASIC Jalapeño domain has more than 1 PB/s of aggregate HBM4 bandwidth, which is significantly higher compared to GB300 NVL72 (576 TB/s). A one-trillion-parameter model using FP4 weights requires about 0.5 TB. So, purely from a bandwidth perspective, the system could read the entire model more than 2,000 times per second. Meanwhile, actual inference performance comes nowhere near that theoretical ceiling, which is why hardware developers do not tend to add HBM bandwidth infinitely.

Smart data movement

Instead, Jalapeño uses what OpenAI describes as a memory-sliced, or NUMA-style, architecture. The chip has 64 core slices, and each of them is paired with its own HBM slice to guarantee predictable latency and bandwidth. OpenAI says this arrangement avoids conflicts associated with a unified memory subsystem and lets frequently used operands remain close to the compute resources that need them. OpenAI does not explain why it chose exactly 64 slices, which likely means it was a sweet spot for the current architecture.

To connect the 64 core slices, OpenAI uses a specialized high-bandwidth, low-latency collective network that moves data coupled to compute operations 'register-to-register, with zero conflicts' in a bid to eliminate several performance bottlenecks. In addition, Jalapeño has a separate general-purpose network-on-chip (NoC) that handles less common communication (e.g., remote/global memory accesses) and provides access to the external scale-up network.

The distinction between these fabrics is substantial. OpenAI describes the general NoC as deliberately more 'anemic than you would expect from a normal chip architecture' as it does not want performance-critical traffic to use it typically. By contrast, the ultra-fast collective network organizes data movement, so operands arrive in registers when needed rather than leaving compute engines and then waiting for memory, network traffic, or global synchronization, which creates internal performance bottlenecks.

In general, it looks like one network is optimized for speed and predictability for inter-core communications, whereas the other is optimized for general use cases. Trying to make one NoC do both would require a much more capable general network, consume more silicon/power, and reintroduce contention.

A different approach

OpenAI's Jalapeño is also designed for the very different types of work that happen during a single agentic inference request.

To explain how it works, let us compare OpenAI's and Nvidia's approaches. Nvidia's standard system-level decomposition is primarily two phases: prefill and decode. Prefill is generally compute-bound (which is why Nvidia tried to assign Rubin CPX with GDDR7 for this one), while decode is generally memory-bound (which is why Nvidia wants to keep GPUs with HBM for this). By contrast, OpenAI breaks the process into three phases: prefill (compute-bound), draft (latency-bound), and verification (bandwidth-bound).

In theory, OpenAI could have assigned each phase to a different type of specialized accelerator. However, the amount of prefill, drafting, and verification changes depending on the model, context length, token efficiency, and software algorithms. As a result, it is hard to predict the number of processors that must be deployed, so it's inevitable that some phases would sit idle. To that end, it makes more sense to develop one balanced ASIC that can do everything.

As a bonus, a universal inference accelerator does not need to move increasingly large KV cache to its peers, unlike highly specialized ASICs, which ultimately means less power consumed.

Chips develop chips

Despite Jalapeño's exceptionally short development cycle, OpenAI says that most of the processor was designed from scratch rather than assembled from existing Broadcom accelerator IP. OpenAI's Richard Ho said the compute die reuses some interface IP, but most of its Register Transfer Level (RTL) was newly written using XLS and Verilog. Meanwhile, development moved remarkably quickly: initial RTL work began in February 2025, the design taped out in November, first silicon arrived in May 2026, and OpenAI had Codex running on Jalapeño that same month.

One reason OpenAI was able to move so fast with its development was its extensive use of AI to assist and optimize the design. More than half of the core was written using the XLS hardware language and compiler infrastructure, while OpenAI's own AI models searched for ways to improve power, performance, and area (PPA). Compared with human 'baseline' designs, OpenAI reports improvements of 56% for a BF16 multiplier, 21% for an FP4 dot-product block, and 10% for an FP32 accumulator, along with 10% and 8% area reductions for the matrix and SIMD units. The company says that AI-assisted optimization even helped squeeze circuitry into a floorplan block that otherwise would not have fit, though OpenAI remains tight-lipped about what circuitry it was.

Jalapeño is OpenAI's first, but not the last, attempt to develop custom inference hardware. The company says its 2^nd Generation already well into development and heading toward tape out, while Richard Ho said during the presentation that Gen 3 is already 'operational,' even though his slide said 'planned.'

Programmability

Because Jalapeño features its unique spatial and sliced architecture, it is programmed differently from Nvidia's CUDA GPUs. OpenAI says Jalapeño can be programmed using a low-level programming environment in the open-source Triton ecosystem. Unlike the latest versions of CUDA, which ensure that its code runs on all Nvidia GPUs and aligns with the tensor-heavy execution model of Blackwell processors and their successors, Jalapeño gives software more explicit control over where data and computation are placed.

Each core has fast access to its local portion of HBM; these cores are interconnected using an ultra-fast network, so the software must be able to determine where tensors are physically located and how they are distributed across the chip. This makes programming the spatial architecture more complicated, so OpenAI also uses AI to find efficient data placement, scheduling, and communication patterns and to optimize kernels for the hardware.

Meanwhile, optimal mapping is architecture-dependent, so once OpenAI changes the number of cores, local-memory organization, collective-network topology/bandwidth, or compute resources in next generations of its accelerators, the old placement and scheduling may no longer be optimal and will require AI tools to perform hardware-specific optimizations again. By contrast, software written for Blackwell will work on Rubin and then Feynman without modifications.

But how good is OpenAI's software stack compared to CUDA? Apparently, good enough, based on performance results published by the company.

Performance

Instead of comparing peak performance numbers, OpenAI used SemiAnalysis' InferenceX benchmark to compare Jalapeño and Nvidia's GB200/GB300 across their complete latency-versus-throughput curves. The company measured how many tokens each system could deliver at comparable user-perceived latency and normalized the results by package power — 700W for Jalapeño, 1,200W for GB200, and 1,400W for GB300 — meaning that while Nvidia's hardware can lead in terms of absolute performance, OpenAI's accelerator leads in efficiency.

Compared to Nvidia GB200/GB300, Jalapeño delivers:

• Roughly 1.5X – 1.9X higher peak throughput per watt
• 1.7X – 3.6X lower end-to-end latency
• 2.1X – 4.1X lower minimum time between tokens (TBT)
• At Nvidia's minimum-TBT operating points, Jalapeño can deliver up to 104.3X higher throughput.
  
  This methodology particularly favors Jalapeño's strength at low latency, so the result is significantly inflated. The 104.3X figure means that at GB300's lowest-latency operating point, Jalapeño can maintain 104.3X higher throughput, not that Jalapeño is 104.3X faster overall.
• OpenAI also noted that its internal models show an even larger advantage for the Jalapeño platform and says applying multi-token prediction to Jalapeño can improve latency by another 3X to 5X at equivalent efficiency.

AI makes chips now

OpenAI used Hot Chips 2026 to fully detail Jalapeño, its first custom inference AI accelerator co-developed with Broadcom. The ASIC relies on a NUMA-style architecture built around 64 memory/core slices, carries 216 GB of HBM4 memory, and has compute performance of up 13.4 MXFP4 PFLOPS at 700W. Being aimed at AI data centers, Jalapeño scales from 128 accelerators per rack to 2,048 inference processor per pod and can provided up to 27 EFLOPS of MXFP4 compute, 432 TB of HBM4, and 32 PB/s of aggregate memory bandwidth per cluster.

While absolute performance of Jalapeño may fall short of what Nvidia's Blackwell or Rubin offer, the company argues that the main advantage of its AI inference accelerator platform is its performance-per-watt achievements as well low latency. OpenAI says its Jalapeño delivers roughly 1.5X – 1.9X higher peak peak-performance-per watt and 1.7X – 3.6X lower end-to-end latency than Nvidia GB200/GB300 in its InferenceX comparisons.

Perhaps the most impressive, or maybe even terrifying, though certainly not unexpected thing that OpenAI revealed is that AI played a major role in Jalapeño's unusually fast nine-month RTL-to-tapeout development cycle and also enabled the company to improve performance, power, and area, of the design. Jalapeño's successor is already heading toward tapeout and OpenAI's 3^rd Generation AI accelerator is already in development.

It has become a tradition that every single quarter Nvidia reports record results that outpace all of its quarterly results before that. This Wednesday was no exception as the company posted revenue of $96.2 billion, which was up 106% year-over-year, due to rising demand for its AI hardware. But such results come at a cost, as the company has to invest massively in its future. In the second quarter of its fiscal 2027, Nvidia had to commit to procuring memory worth up to $160 billion, which includes its memory supply pact with SK hynix.

Nearly $100 billion revenue per quarter

For the second quarter of Nvidia's FY2027, which ended on July 26, 2026, the company's GAAP revenue hit a record $96.221 billion, up 18% quarter-over-quarter (QoQ) and 106% compared to the same quarter a year ago. Nvidia's net income totaled $59.688 billion, up 126% year-over-year (YoY), as its gross margin reached 75.0%. Sales of Nvidia's Compute & Networking hardware reached $88.299 billion, up 18% sequentially and 114% YoY, whereas sales of its graphics hardware hit $7.922 billion, up 12% sequentially and 46% year-over-year.

"AI has reached its inflection point," said Jensen Huang, founder and CEO of Nvidia. "AI is doing useful work. Its tokens are productive and profitable. Now, compute is revenue. And demand is accelerating. […] We have a golden age of new AI labs and startups, multiple frontier labs scaling in parallel, a thriving open-model ecosystem and physical AI coming online […]. The AI infrastructure buildout is at full steam. Vera Rubin, now in full production, was built to power exactly this moment."

Nvidia's results were driven by sales of its data center-grade AI hardware as various customers bought $89.023 billion worth of equipment, an increase of 18% sequentially and a rise of 117% compared to the same quarter a year ago. Hyperscalers purchased $48.710 billion worth of hardware from Nvidia (up 102% YoY and 13% QoQ), while revenue from AI Clouds, Industrial and Enterprise climbed to $40.313 billion (up 138% YoY and 25% QoQ), an indicator that while hyperscalers still purchase more equipment from Nvidia, the ACIE segment is growing faster. Sales of Nvidia's Edge Computing products were $7.198 billion (up 27% YoY and 13% QoQ), which means that sales of graphics products for PCs were strong despite shortages of GPUs and memory.

Commitments total $279 billion

Nvidia expects demand for its products to remain strong in the coming years. To meet that demand, the company increased its long-term purchase commitments from $119 billion in Q1 FY2027 to $279 billion in the second quarter. Typically, Nvidia's long-term supply commitments included pre-payments and commitments for wafer processing and advanced packaging at TSMC, as well as for HBM memory made by DRAM makers. This time around, Nvidia explicitly says that the bulk of the commitments are 'primarily related to the procurement of memory.'

Such huge commitments indicate that the company projects massive demand for its data center AI products in the coming years. During the conference call with financial analysts and investors, it indicated that its customer forecasts point to doubling demand next year, but Nvidia currently believes its supply chain can support about 70% growth.

"Even though our demand is much greater than 70%, our supply allows us to confidently deliver 70%," Huang said. "The unconstrained would be a lot, a lot higher. […] We have secured a lot of supply, but we just need a lot more."

To that end, the $279 billion supply commitment should be interpreted as not a precautionary inventory-building, but a strategic move to ensure shipment growth. Nvidia is effectively reserving memory and other capacity because it expects demand to exceed what the supply chain can deliver through at least the end of FY2028, as its management explicitly says supply will remain a bottleneck at least through FY2028.

$108 billion per quarter envisioned in Q3

For the third quarter of FY2027, Nvidia expects revenue of approximately $108 billion, ± 2%, with no data center compute revenue from China included in its outlook due to uncertainties with export and import licenses. The company projects a GAAP gross margin of around 74% and expects GAAP operating expenses of approximately $9.2 billion.

OXMIQ Labs, a GPU IP company, revealed at Hot Chips 2026 that High Bandwidth Flash (HBF) cannot replace High Bandwidth Memory (HBM) across the vast majority of workloads. For some, HBF could emerge as a specialized memory tier for huge but relatively cold datasets. For others, HBF can do more harm than good.

When SanDisk unveiled its High-Bandwidth Flash (HBF) concept in early 2025, the technology pledged to equip AI accelerators with terabytes of relatively inexpensive memory and reduce the need for traditional High-Bandwidth Memory (HBM), a promise that raised a number of doubts from the very beginning.

The emerging HBF specification includes three performance grades. Grade 1 uses an 8-Hi 256GB NAND stack with an 8 GT/s UCIe interface and 384 GB/s bandwidth. Grade 2 uses a 512GB NAND stack with a 16 GT/s UCIe interface and supports 1.536 TB/s bandwidth. Grade 3 reaches 3.072 TB/s using 32 GT/s UCIe 2.0 while retaining the same 512 GB capacity.

Since HBF relies on 3D NAND, it supports read block sizes between 64 bytes and 4 kilobytes, 4KB writes, and 4KB page sizes. While HBF Grade 1 can barely compete against contemporary HBM, HBF Grade 3 can compete against HBM4E, though we have no idea when such memory will be available. However, the main feature of HBF is not necessarily performance per se, but 8 – 16 times more capacity than HBM at roughly the same cost.

Indeed, OXMIQ believes that HBF should be viewed as a high-capacity memory technology rather than inexpensive HBM. Memory economics depend not only on how many gigabytes an application needs to store, but also on how quickly those bytes must be delivered to the processor. As bandwidth demand rises, adding inexpensive but relatively slow HBF eventually becomes less economical than using HBM, according to estimates by OXMIQ.

Cheap memory =/= cheap tokens

OXMIQ demonstrated the trade-off by modeling a 72-GPU rack running the 1-trillion-parameter Kimi-K2 model at FP4. At cost and power parity, an HBM-only configuration provides 20.7 TB of memory and 1,584 TB/s of aggregate bandwidth. Replacing HBM with HBF increases rack capacity by 14 times to a whopping 294.9 TB, but reduces aggregate bandwidth to 922 TB/s. A hybrid configuration with HBM and HBF provides 89.3 TB and between 279 TB/s and 1,418 TB/s, depending on workload conditions. The difference between HBM and HBF bandwidth is the reason why HBF looks excellent when memory capacity limits the system. However, HBF eventually loses when bandwidth/throughput becomes the limiting factor.

In OXMIQ's model, an HBF-only configuration enables each GPU to hold its own Kimi-K2 instance and run 72 model instances per rack. Whereas an HBM-only configuration requires eight GPUs to hold each model instance (meaning compute performance gets wasted) and can therefore run only nine instances per rack. This makes HBF particularly attractive when memory capacity determines the number of GPUs required. However, as the number of simultaneous users and their token-generation rate increase, HBF's lower bandwidth becomes the bottleneck, while the HBM-based rack can make better use of its substantially higher memory bandwidth and ultimately deliver lower cost per token, according to OXMIQ's model.

As a result, HBF can dramatically reduce the number of GPUs needed simply to accommodate a very large model (i.e., enable one HBF-equipped GPU to do the capacity job of eight HBM-equipped GPUs). Nonetheless, if the objective is maximum inference throughput from a fully utilized rack, HBM may remain the better, more economical choice. At the end of the presentation, OXMIQ concludes: 'HBM for the rack, HBF for the box.'

Niche memory?

Although HBF does not benefit all AI workloads and may even harm the performance of many, there are applications that can benefit from a surplus of local memory.

Mixture-of-experts (MoE) models appear to be particularly suitable for HBF. OXMIQ's Kimi-K3 example has 1.56 TB of weights, of which 1.45 TB, or 93%, consists of MoE expert weights. Since only selected experts are activated for each token, this enormous pool is largely write-once and relatively infrequently read. OXMIQ proposes keeping such experts in HBF while placing the remaining, frequently accessed weights in HBM.

Additionally, more local capacity could also reduce communication between accelerators. Conventional expert parallelism distributes experts across GPUs and requires all-to-all communication at every layer. OXMIQ claims that inexpensive HBF capacity could allow considerably more experts to reside locally, reduce the number of expert-parallel shards, and reduce network traffic. In this case, HBF effectively trades memory capacity for interconnect bandwidth and power consumption.

Long-context inference is another potential use case. Sparse-attention models access only a small portion of their large KV cache during each decoding step, which allows the rest to remain in slower HBF memory. OXMIQ believes that HBF could store this large KV cache while the accelerator fetches only the data needed for each step from HBF to HBM.

The HBM-as-cache idea has a serious limitation. Intuitively, one would put popular experts in HBM and cold experts in HBF. Such a strategy works mainly at low batch sizes or when similar queries can be deliberately batched. As batch size rises and queries become more heterogeneous, however, expert popularity flattens, and the workload accesses a broader range of experts, according to OXMIQ. The working set can then outgrow the relatively small HBM cache, which results in more frequent expert transfers from HBF and reduces the performance benefit provided by HBM caching.

The hardest part

OXMIQ does not expect HBF to work simply as slower GPU memory. Instead, it proposes using HBF in place of host DRAM to store large amounts of less frequently accessed data, such as MoE experts and KV cache. Frequently used data would remain in HBM, while even colder data could still be kept in remote memory or SSDs. This certainly contradicts SanDisk's original vision for HBF: sitting next to AI accelerators. Furthermore, adding HBF support will be complicated on many levels.

The software side of HBF is particularly complicated. To achieve maximum bandwidth, HBF requires large transfers — 64 KB reads and 1 MB writes — and data is moved through DMA rather than the CPU/GPU cache hierarchy. When HBF and HBM are used together, software must also decide which data goes into each memory type and manage HBF's limited write endurance.

Meanwhile, current inference software is not ready for such a configuration. OXMIQ says vLLM would need dedicated HBF support to manage memory allocation and data placement, prefetch data before it is needed, and monitor flash endurance, which requires a major software overhaul. An effort like this has to be a joint effort between the HBF hardware vendors, AI accelerator vendors, and inference-framework developers.

At the lowest level, AMD, Nvidia, and other accelerator vendors would need to provide the hardware/driver/runtime mechanisms for efficiently moving data between HBF and HBM. Then vLLM developers, who work with vendors, would implement the higher-level memory allocator and policies that decide which experts/KV blocks live in HBM and which reside in HBF, when they should move, and how to hide HBF latency.

On the one hand, if AMD or Nvidia adopt HBF, they will provide its partners with everything needed to use it, and while this would take time before everything works as intended, this is a straightforward way to add HBF support to AI platforms. On the other hand, the biggest question is whether hardware vendors like AMD or Nvidia need HBF. As per OXMIQ, HBF's advantage is limited to select use cases, so it may not make sense for AMD or Nvidia to support it universally, especially keeping in mind that managing multi-tier memory hierarchy is hard.

SambaNova is perhaps the most obvious candidate to support HBF. Its SN40L already uses a three-tier hierarchy: SRAM => HBM => DDR, with up to 520MB of SRAM, 64GB HBM, and 1.5 TB of DDR. Conceptually, HBF could become another tier or replace some of that DDR capacity. Then again, this is merely speculation.

HBF remains a nascent technology

While we still have a lot to learn about how HBF works, OXMIQ's model suggests that HBF has a much weaker general-purpose value proposition than the original claim made in early 2025 suggested. It is not useless: it is a specialized solution whose strongest applications depend on particular workload characteristics.

The fundamental problem is that HBF solves memory capacity, while modern AI accelerators are frequently constrained by memory bandwidth. OXMIQ's simulation makes this rather obvious: HBF provides about 14X more memory capacity but only 0.6X the aggregate bandwidth of HBM. Once the workload becomes sufficiently bandwidth-intensive, the enormous capacity stops offsetting the bandwidth deficit.

While the hybrid HBM+HBF solution makes sense for some use cases, it is not a magic fix. When HBM is used as an expert cache, heterogeneous requests at larger batch sizes flatten expert popularity, cause the workload to touch more experts, and reduce cache efficiency dramatically.

For now, HBF has three particularly compelling use cases: reduce the number of GPUs required simply to fit huge models, store massive but infrequently accessed MoE expert pools, and keep large KV caches for sparse long-context inference. For MoE models, its large local capacity could also reduce expert parallelism and expensive all-to-all communication between GPUs. In all three cases, HBF makes sense because capacity requirements are enormous while bandwidth demand remains relatively low.