Eight years after GlobalFoundries abandoned the development of its 7nm FinFET technology, the company is preparing to return to 7nm-class performance, this time by going via a different route. Its FDX Fusion process, built on FD-SOI (fully depleted silicon-on-insulator) technology, promises 7nm-class performance using advanced planar transistors, with no EUV lithography necessary.

In an interview with Tom's Hardware Premium, GlobalFoundries' Sudipto Bose, vice president of the FD-SOI business unit, shared new details about its FDX Fusion technology, including its 8nm-class logic density, advanced planar transistors, manufacturing costs, and plans to begin commercial production in 2028. The company also explained how it intends to compete with conventional FinFET technologies and why it believes FD-SOI has a future beyond the 22nm-class generation. Some elements of this interview transcript have been edited for flow and clarity.

Sudipto Bose: I have been at GlobalFoundries (GF) for a little bit over six years, and I have been in the industry for 25+ years. I spent the rest of my career at Texas Instruments (TI), so it's really two jobs that I have done: TI and GF. Half and half engineering and business. I spent a lot of my business days in the automotive segment. This was what I was doing at GF when I joined, and now I have the FDX product line role.

Sudipto Bose: A little bit on the history of FDX at GF. GF has been investing in FD-SOI for a long time. It started [these efforts] before I joined. So I would say almost eight years now. And a lot of the investment thesis that drove us towards FDX Fusion is based on the traction that we have in the market today, right? We have quite a few customers who are ramping up. And I say quite a few; this is like high double-digit customers in the nineties that are ramping up right now.

Applications for FDX Fusion

Anton Shilov: What specific types of chips and devices is FDX Fusion designed for? Which application will benefit most from its capabilities?

Sudipto Bose: FDX Fusion will try to enhance the applications in which we play today. What do I mean by that? If you look at our current customers, they are designing chips, everything to do with connectivity. When I say connectivity, think of Wi-Fi, Bluetooth, cellular, satcom, all of that. So that is one class of customers.

There's another class of customers who are designing processors at the edge, so these are MCUs (microcontroller units) with some level of inference sitting inside. Think of customers like Alif Semiconductors. So that is another class: MCUs at the edge.

Then in automotive, we have a disproportionate exposure to radar, and this is because of the eighty-one gigahertz performance that FDX brings to the table. So we will engage with them as they try to enhance their portfolio. We also have an automotive MCU, but radar is where you will see a lot of press releases that we have done.

Last but not least, we also have exposure in the data center segment. This also goes back to the fT/fmax, the high-performance RF that we have, which is a good candidate for designing TIAs and clock recovery circuits.

Anton Shilov: By applications inside data centers, what exactly do you mean? CPUs?

Sudipto Bose: Not CPUs. It is in the connectivity space. So, if you think about GF's focus, we are very focused on two things in data centers: power and connectivity. So in the connectivity space, we have silicon photonics, or turning electrons into photons. But then when you receive them, you have the optical diode, again, a GF silicon photonics technology. After that, you need circuits that will amplify those weak electrical signals and drive them to the compute chip. This circuit, which amplifies the weak electrical signals, is right now being done by GF silicon-germanium, but once FDX Fusion is there, we'll offer them both [as] options. And so, to be very specific to your answer, these are data/signal paths inside the data center that feed into CPUs.

7nm-class FD-SOI node

GlobalFoundries' FDX Fusion is a new manufacturing technology that promises 8nm-class logic density and 7nm-class power and performance without EUV lithography or FinFET transistors, which greatly reduces design costs and manufacturing costs at the cost of significantly lower transistor density compared to 7nm-class nodes.

Instead, the process relies on advanced planar fully depleted silicon-on-insulator (FD-SOI) transistors, strained silicon substrates, and aggressive optical patterning techniques to achieve transistor dimensions comparable to those of conventional 8nm-class FinFET nodes.

FDX Fusion also retains support for adaptive body biasing and combines high-density digital logic with RF, analog, and embedded memory capabilities. The technology will be manufactured using deep ultraviolet (DUV) lithography, although its tighter gate and metal pitches will likely require extensive multipatterning for the most critical layers.

Anton Shilov: What are the key innovations of FDX Fusion compared to predecessors and other nodes that are currently used?

Sudipto Bose: The key things that we're improving from the current-generation FDX, the first one is fT/fmax, this is 500 GHz, or 0.5 THz fT/fmax. This helps the first segment that I talked about, which is connectivity. This helps automotive radar, and this definitely helps the data center segment as they try to improve data speeds. So this is not really competing with silicon germanium. Think of it as silicon germanium at the very high end, and FDX in the 100 – 200 Gb per lambda space. That is one. The second one is the inference at the edge. So we can call it physical AI, and we look at physical AI as sense, think, act, and connect. But the kind of feature set we are putting in starts with improving the digital gate density. This is 2.2 times more dense than the current generation FDX (22FDX and 22FDX+).

Sudipto Bose: We are putting in a lot of flavors of eNVM, a lot of flavors of SRAM, because in edge AI, and in fact for any AI, the real game is how much memory you can pack without increasing the cost. So we are adding a lot of flavors of those. The way we architected FDX Fusion is that we set a goal of how much performance we can deliver to our customer base without increasing their operating expenses.

If you look at classic 7nm, 6nm, they require EUV tools. The mask set is costly; the tool chain is costly. The FDX Fusion platform that we've built isn't going to use EUV tools. It is also based on planar technology. So there are two advantages to this. One is that we can support a much more competitive mask set price compared to 6nm. We can also offer [customers] a lot more flexibility in terms of cycle time and in how many places we manufacture, because FDX Fusion does not need EUV tools.

So, to summarize the answer? We are trying to improve RF and analog performance, digital gate density, and the classes of memory that we offer. What applications are we trying to target? It is connectivity, edge AI, high-frequency mmWave, automotive radar, and definitely applications inside data centers.

Anton Shilov: You just mentioned transistor density. The press release says that it has more than twice the transistor density of the original 22FDX process, but you never actually published a transistor density number for this. Could you share any numbers?

Sudipto Bose: I will share a number with you. But I will also give you a little bit of context on how our customers look at our technology portfolio. If you look at the current generation, the one that we are manufacturing today, the one where I said we have 90+ customers ramping. Not designing, ramping. This basically comes from the flexibility of FD-SOI. You have the box, the depleted channel, and you can use body bias. So we have customers who are able to achieve 16nm-class power and performance with 22FDX. What do I mean by 16nm-class power and performance?

It essentially means that although our gate density is not as close to 16mm, when you look at the system-level requirements like CPU clock, but think of it as TOPS per watt, we are matching 16nm; in some cases, we are matching 12nm-class.

[...] If I were sitting in a time machine and went back seven years, instead of calling it 22FDX, we could have called it 16FDX, right? Or we could have called it 16nm-class FDX. So with that analogy, if you come to FDX Fusion, our gate density of FDX Fusion will be exactly the same as the industry's 8nm standard today.

It is 14 million gates per square millimeter; that is the density.

Note: Assuming he uses a two-input NAND gate as its reference, each gate contains four transistors, which translates to 56 MTr/mm², which is comparable to what Samsung's 8nm-class nodes use.

Sudipto Bose: Now, why do we call it 7nm-class? Or we actually thought of calling it 6nm-class, but then we said, let's wait for some silicon before we go too far ahead. It is because digital gate density is one aspect of a solution. It defines your physical size, the die size, and that is great. But then you need power and performance. And with the adaptive body bias (ABB) capability that FD-SOI has, and with the standard cell metallization innovations that we have brought in FDX Fusion, once a device is done and you again look at TOPS per watt, it should be equivalent, if not better, than what 7nm can achieve. That is our product target. So for a customer, the value it brings [customers] is: 'I do not have to use an EUV tool line. I do not have to use a mask set that costs many millions of dollars.'

I have something which costs a few millions of dollars, has great cycle time, but at the same time, I am getting TOPS per watt, which is similar to or better than 7nm. The die size might be bigger, but again, it should not be no bigger than what 8nm is today. And that is the messaging to the industry; that is why we say 7nm-class instead of saying, 'Hey, this is 7nm density.' We are trying to reflect what our customers have told us. That in the edge world, in the physical AI world, the size of the die is one aspect, but if the die does not meet the power requirement of the application, then the whole system will not function. So that is the push.

Anton Shilov: That is perhaps why you actually called the technology FDX Fusion instead of using some fancy number.

Sudipto Bose: Yes, because the moment we put a number [out], people put us in a box. And we want to give customers the optionality of, 'Listen, you want to design a transimpedance amplifier using the fT/fmax that we have? That's an analog circuit. No one cares about digital gate density. Go build it.'

'You want to build a simple MCU, which is just SRAM and IOs? We have 14 million gates per square millimeter. Go build it.' 'You want to build a mixed-signal design like a single-chip radar, Wi-Fi, a satcom digital beamformer? Here are the few other knobs that you can turn to get the best PPA or the best system performance that you need.'

That is why we chose the name Fusion; we are trying to imply [that] we give you many options. It is the combination of all the good things the world needs to design the physical AI dream that we have put in front of ourselves, like the whole stack concept of 'sense, think, act, and connect'. Let us see if it sticks. I think it is a bold move for us to go against the grain of the way the foundry industry typically names its platforms, but we feel pretty strong about it.

Anton Shilov: So, you shared the gate density number, but could you maybe also share things like contacted gate pitch, metal pitch as well?

Sudipto Bose: In time. The reason I mention that is there is a little bit of IP involved. We want to get the first silicon out, engage with a few customers before we publish the CPP and the M(etal) layers. […] We are pushing the limits of patterning and coloring as well as gate oxide engineering to get the best CPP and metal pitches, which will enable this level of density of gates. That is, I would say in terms of R&D dollars just at a very high level, 50% of R&D dollars is on the transistor itself because we are doing strained substrates. There are multiple techniques we are using to improve the PFET and NFET performance. The other 50% is all on CPP and metal pitches.

Anton Shilov: So, are those contacted gate pitches and metal pitches comparable to conventional 7nm class FinFET process technologies?

Sudipto Bose: Comparable to 8nm.

Anton Shilov: When we talk about 8nm, basically speaking, there is only one company that actually produces chips using an 8nm-class technology. That is Samsung Foundry. TSMC and Intel Foundry do not have 8nm-class technologies. So I suppose that we should compare it to Samsung's 8nm node, right?

Sudipto Bose: That's a fair guess.

Anton Shilov: When it comes to power consumption improvements versus 22FDX and 22FDX+, how much lower power can we get using the new FDX Fusion node?

Sudipto Bose: It depends on the application, but I understand your question. So if you just normalize with [iso performance and iso power], I am giving you an answer with adaptive body bias included. If you consider current-generation FDX as the base point, the goal of FDX Fusion is to get 30% higher performance and 40% lower power. Again, it is really application-driven [in] how low you can go. But if you take the standard core, our goal is to get at least a 20% improvement.

Anton Shilov: What types of chips do you expect to benefit most from the FDX Fusion technology? You mentioned connectivity, edge AI, high RF, automotive radar, and connectivity applications inside data centers. What about application-specific AI accelerators, because you mentioned edge inference?

Sudipto Bose: From the STAC — sense, think, act, and connect — framework point of view, let me give you an example. Think of a humanoid, or a car — major applications that need to see. It needs to see and then infer what the environment is like. So the class of chips that do this vision processing at the edge to infer the surroundings will definitely be supported with FDX Fusion. The class of chips that will hear, do voice recognition, and, from voice recognition, draw conclusions, we definitely want to support [them]. Now, at the data center right now, as I said, our play is connectivity. Just translating optical to electrical signals.

If a customer wants to use a chiplet, which has a lot of memory, think of analog in-memory compute along with an inference engine, by all means we will support [such applications]. We will work with customers to see how we can play in that compute ecosystem in the data center. But in terms of pure focus, the first 10 customers that we are engaged with are either at the edge, or they are in the connectivity piece inside the data center.

Note: For those of our readers who are not familiar with ABB, this is a technique that dynamically adjusts a transistor's threshold voltage by changing the voltage applied to the transistor body. Forward body bias reduces threshold voltage to improve performance, while reverse body bias increases it to reduce power leakage. This enables chips to optimize performance and power consumption according to workload requirements. ABB is one of the key advantages of the FD-SOI technology.

Anton Shilov: Since you mentioned this, does FDX Fusion retain the active body biasing capabilities of its predecessors?

Sudipto Bose: It is an inseparable part of the platform, yes. We will launch this platform in a way that customers can use it.

New tools required

Anton Shilov: You also mentioned makers of wafer fab equipment. Will FDX Fusion use existing manufacturing equipment at the Dresden facility, or will it require substantial investments in new lithography, deposition, etching, and metrology tools?

Sudipto Bose: It will require new tools. Substantial is a relative term. If you see the amount of money being invested in semiconductors, the term 'substantial' has changed. We are going to get new tools, which is why we combined the FDX Fusion announcement event with the topping off of the Sprint expansion project. That's why we had all the luminaries from the German and the European government. There will be tool investment; we will be buying tools from the vendors. How much of it is going to be litho versus etching? Time will tell, but for sure we need new tools compared to what we have today.

Anton Shilov: But will you essentially need to completely re-equip the Dresden facility to use FDX Fusion? What percentage of the tools you have can be reused for FDX Fusion?

Sudipto Bose: We can get back to you on that exact answer because I do want to give you a proper answer, rather than a high-level answer. But I will tell you where the targets are. With the front end, the transistor fabrication tool chain, my target is to reuse as much as we can.

Anton Shilov: You also mentioned that you plan to begin manufacturing FDX Fusion in 2028. But does this refer to risk production, initial customer production, or high volume manufacturing?

Sudipto Bose: Initial customer production.

Anton Shilov: When do you expect the technology to reach mature yields and meaningful production volumes?

Sudipto Bose: I will give you my target, and then the industry will define it because we are a part of a bigger ecosystem. 2030 is when we want to get to high-volume manufacturing with FDX Fusion. But again, it depends on the first applications and the first few customers.

Readiness

Anton Shilov: Speaking of customers, you probably already have customers who are committed to production, haven't you?

Sudipto Bose: We have customers who are committed to building a chip. Of course, we have to deliver to their specs before they go to production.

Anton Shilov: I suppose the customers that you mentioned in the press release like BMW, Bosch NXP, Siemens, and Tesla, they are all plan to build chips on this technology.

Sudipto Bose: […] They have been pushing us for the last few years to do something like this, and they have given us requirements. Now we are doing it, and we have to show them what we can [deliver]. So there is a lot of push that we have received from the industry, from these companies. When I say these companies, the supply chain that leads into these companies to deliver something which will work at the edge. So we are racing against time to show them something that will meet the specs.

Anton Shilov: GlobalFoundries plans to release the initial FDX Fusion PDK in mid-2027. But when do you expect complete digital, analog, and RF design flows to become available from the three major EDA vendors?

Sudipto Bose: Yeah. I wish I could tell you… Right now we are in discussion with all the major primes, so we are in the request for information/request for quotation (RFI/RFQ) phase, but we have started discussions with the major EDA vendors. It has been almost six to nine months now.

Anton Shilov: But you do expect all the leading EDA vendors to support FDX Fusion in eight to nine months?

Sudipto Bose: Of course. We are going to engage with the whole ecosystem that we have, and once [the PDK is out], we have to support a proper flow not just for chip design, but also IPs that are required and everything else around it.

Anton Shilov: So how extensive will the initial FDX Fusion IP ecosystem be? Will customers have access to silicon-proven standard cell libraries, SRAM compilers, embedded non-volatile memory, interface IPs, maybe analog and radio frequency building blocks before 2028?

Sudipto Bose: Yes. In the first two years, we are going to engage with pilot customers. Think of these as early adopters. We have early adopters listed, and we will design standard cell, I/Os, and SRAM [...] needed for everything, so we will have those. But then the complex IPs, like PCIe Gen 4/5 or LPDDR6 or a DisplayPort, will be dictated by the first few applications that will ramp. FDX Fusion for us is the beginning of a journey. We have been on the journey of 22FDX for almost eight years. I envision FDX Fusion to be more than that. Even on our current platforms, we keep enhancing our IP portfolio. So I expect us to be adding IPs to FDX Fusion over the next ten years.

ARC, MIPS, and Fusion FDX

Anton Shilov: GlobalFoundries also highlighted its ARC and MIPS processor IP portfolios and RISC-V expertise as part of the FDX Fusion offering. Do you plan to develop processor cores and AI accelerators specifically optimized for FDX Fusion? IPs specifically optimized for FDX Fusion? Or will you primarily port existing IP to the new process?

Sudipto Bose: MIPS is an internal customer and a partner, and we will engage with them, and they will launch a platform for physical AI that is fine-tuned, in a combination of what they have and what FDX Fusion has. ARC and MIPS are key pieces of the strategy. Having an internal customer like that just enhances our development cycle by 5X because now they can start developing fast turns of test chips and give us feedback. We did not have this capability in the past. Now we do. Once they are ready, they will start announcing stuff.

Anton Shilov: So essentially, you will both port the existing IPs to the new node, but also MIPS will likely develop something brand new specifically for FDX Fusion.

Sudipto Bose: Yes.

Costs

Anton Shilov: How will the manufacturing complexity and cost per transistor of FDX Fusion compare to 22FDX+, your 12nm FinFET technology, and conventional 8nm FinFET technology?

Sudipto Bose: This would be the most advanced planar transistor that the world has seen, the most advanced non-EUV-based manufacturing line that the world has seen. So, I would say significantly more complex than our current 22nm-class FD-SOI line. More complex than what we have on the 12nm FinFET line. We are working with every tool vendor that you can think of as part of this program, and we have given them the challenges. It goes back to your question about our contacted gate pitch and metal pitch. So, we have had multiple workshops with them over the last few quarters, and each one of them is proposing a tool recipe that they think will get this to a nice and solid yield.

Sudipto Bose: So, I guess the answer to your question is: firstly, it is definitely complex, and secondly, we are really using the entire ecosystem available to us to come up with tool configurations that will deliver this. All of this is going to happen in Dresden. We have to be competitive, so price is always dictated by the market. Our goal is to have a running cost that is significantly better than a 7nm or a 6nm class of design (due to planar transistors and due to lack of EUV masks). After that, we will work with our customers to figure out what makes sense. But you are right, the value that we want to bring in is, 'dear customers, you do not have the same operating expenses load, meaning the cost of tape-out is less than 6nm.'

And you can do multiple tape-outs because this class of devices is not something where you can design one part and use it for 15 applications. You really need 15 devices for 15 applications. So, we definitely enable that. Then, when it comes to manufacturing cost, it is a discussion with our customers. We have various business models, but the goal is to make sure it is a win-win. At the end of the day, the lower the cost we are, the more flexibility we can provide to our customers. The non-EUV path is one of the things that was dictated by our decision that we must keep this a cost-competitive platform.

Anton Shilov: So, cost-wise you want to be competitive, but it's likely comparable to 8nm.

Sudipto Bose: I will have a better feel once we are complete with what we call our M-cycles inside the fab. But I would say my internal target is that we have to be better than that.

The future of FDX

Anton Shilov: GlobalFoundries describes upcoming technology as its 1st Generation of FDX Fusion. Does this mean that you envision subsequent generations with high transistor density and performance? Maybe you can share some preliminary targets or timelines for the next node?

Sudipto Bose: We have listed quite a few innovation steps that we want to enable on this platform. The FDX Fusion definition is based on the ones we believe we are more confident that we will be able to deliver in the timeframe that we have said. We have kept a few things in the innovation lab, and they are pushing the boundaries of a few things like eNVM, EDA routing, chip folding, 2.5D integration, which, once they mature, will define what the next version of FDX Fusion will look like. I do not have a timeline for the next version of FDX Fusion, though.

As we proceed through the development phase, I would say early 2028 to mid-2028 is when I expect to have a better view of when the next version will be launched. And this is also based on feedback we will get from customers. Because what we have right now is our first silicon, which is running in the lab, which we will show to customers. They will give us a lot of feedback. I am sure we will get a few things right, and at the same time, we will get a few things not so right. And that feedback, along with a few of the innovation topics I mentioned, will dictate what the next generation is going to look like. Stay tuned!

Anton Shilov: One of the reasons why I aksed about next-generation nodes is partly because TSMC typically shares its process technology roadmaps with new nodes well before it releases early PDKs for these nodes. Given that FDX Fusion is now GF's most advanced logic process, with capabilities comparable to 8nm-class technologies (i.e., more advanced than 22FDX or bulk 12nm FinFET), how frequently does GlobalFoundries plan to introduce new process technologies, and how far in advance will it disclose its roadmap?

Sudipto Bose: I would say, we are doing advanced development across the board. If you look at the work we are doing on silicon photonics, on packaging, on power transistors like GaN, RF GaN, Power GaN, these are all pretty advanced. But yes, you are right: in what the world understands as a classic, let's say, high-density process, FDX Fusion is the most advanced. We typically announce or update the industry about our roadmap every year at the GlobalFoundries Technology Symposium. Like this year at GTS, we announced FDX Fusion. So, I would say stay tuned for the GTS sessions that we have, and typically every year we do it in September or October.

CEA-Leti involvement

Anton Shilov: CEA-Leti describes FDX Fusion as a single-digit FD-SOI node. How closely is this new technology related to CEA-Leti's own research in 10nm and 7nm with their SOI nodes?

Sudipto Bose: The platform that we have right now is the outside of the substrate engineering work that we are doing with Soitec and CEA-Leti; the rest of it is GF inherent IP at this point in time. So we are bringing in the knowledge that we have from current-generation FDX, the knowledge that we have from the work that we did in 7nm before we stopped it, the work that we have done on 12nm. So it is bringing in all the innovations across all the GF fabs to figure out what is the best that we can offer. Does it mean that we will not look at what CEA-Leti has in the future? I do not have an answer right now. But for now, FDX Fusion is a very GF innovation-driven effort.

Anton Shilov: So you did not use pre-competitive IP from CEA-Leti to develop FDX Fusion? Is it a completely internally developed node?

Sudipto Bose: Correct.

Anton Shilov: The press release mentions innovations in substrate engineering along with endorsements from CEA-Leti and Soitec. What exactly does that involve, and how does it improve transistor performance? What role do Soitec and CEA-Leti play in developing FDX's strained silicon substrates, and how close is this technology to mass production?

Sudipto Bose: GlobalFoundries is working with CEA-Leti and Soitec under the FAMES program to develop strained silicon substrates for FDX Fusion. The goal is to improve charge carrier mobility and, consequently, transistor performance. Since FD-SOI technology relies on specialized silicon-on-insulator wafers supplied by Soitec, the three organizations are developing ways to introduce strain into these substrates and make the technology suitable for high-volume manufacturing. The approach has already demonstrated its viability in the laboratory, and the partners are now refining the manufacturing process to prepare it for commercial production.

[Session ends]

A Pat Gelsinger-backed Georgia Tech spinout, Nagare Labs, says its Z2RAM can put SRAM-speed memory, at DRAM density, directly on top of AI chips. The founders’ own papers show a fast-improving cell that, tested up to 85 degrees Celsius, holds data for over 300 seconds. Gen 1 is projected to have 5x SRAM density with six stacked layers, 14x DRAM speed, and 3x less read energy than SRAM.

AI chips require a lot of bandwidth, and it has been challenging to get sufficient yields of high-bandwidth memory (HBM) to feed them. Even when manufacturers can get it, some reportedly plan to settle for fewer layers for yield reasons, and heat is another. Heat is also why Samsung’s zHBM, which stacks DRAM directly on the processor, is planned at only about four layers.

Alternatives include high-bandwidth flash, still in development, which stacks NAND like HBM and would sit beside the GPU, or SRAM stacked directly on the die, which is less dense and more expensive for the capacity, but also faster. DRAM, which is more capacious, can sit on top of the compute, but heat limits how hard the logic underneath can run.

That limit is already shaping chipmakers’ design path for stacked memory. Micron’s vHBM plans, for example, include heat-spreading structures. With HBM stacked on a logic die, and DRAM needing to be kept at or below 95 degrees Celsius, the logic’s heat output is capped at 220 W/cm², or 300 W/cm² with better thermal vias, according to a 2025 simulation by co-founder Shimeng Yu’s group. Nagare Labs says peak compute has grown 70% a year over the past three decades, against 20% for memory bandwidth.

The company describes its Z2RAM as “Two transistors and a shield. No capacitor,” where a write transistor places a charge on a storage node and the shield blocks noisy neighbors. The read transistor can sense without draining. In a gain cell like this, the read transistor’s gate capacitance holds the charge, so reads are non-destructive and the cell avoids DRAM’s write-back. Nagare aims for well under a picojoule per bit.

Nagare builds Z2RAM by depositing its layers on top of the accelerator and patterning them “together on one die,” much as 3D NAND flash scales by adding layers. There’s no interposer and no bonds between the memory layers, which is part of the secret sauce. One lithography exposure covers several layers at once, and standard 300 mm tools with DUV do the job, with no EUV required. The current roadmap is aiming at over 100 layers with “hundreds of thousands” of vertical connections.

Retaining data at higher temperatures is the challenge, and one the founders have probed repeatedly with their testing. A 2020 paper from co-founder Suman Datta’s group, on a tungsten-doped indium oxide two-transistor cell, had retention of 1 second at 25 degrees Celsius and just 300 milliseconds at 85°C. An update in 2025, which has Datta as a co-author, adds a third transistor and removes the gate overlap from its transistors, managing over 1,000 seconds at 25°C, up from 200 seconds with overlapped ones. It also simulated a GPU L2 at twice SRAM’s capacity but in the same area with 75–80% lower energy-delay-area product, a combined score that multiplies energy, delay and area.

Six months later, both founders showed a “folded asymmetric boosted” three-transistor cell that held data for over 300 seconds at 85°C, as compared to only 100 milliseconds for a conventional three-transistor design. That’s still below the roughly 95°C that Nagare says DRAM must stay under, so neither the founders’ published cells nor Z2RAM have shown retention above that line yet. The boosted cell is also “refresh-free,” which means data in the GPU’s last-level cache, profiled from AI workloads, doesn’t have time to decay before it is overwritten.

Physical space is also limited for this application, and the founders project their boosted cell at 0.0168 µm² at 7nm, compared with 0.0199 µm² for a high-density SRAM cell on TSMC’s 3nm (N3) process. A separate study from Yu’s group found that a four-tier, 256MB cache of two-transistor gain cells at 7nm could reach 5.7x the bit density of 7nm SRAM in the same area, in simulation. However, the return on investment falls off past seven or eight tiers because masks scale with layers. Nagare Labs’ claim of single lithography would potentially bypass this limitation.

That has not yet been proven, and nothing published yet shows it. “Where we are is literally lab prototypes,” Datta told The Register, adding that sampling of Z2RAM tiles is targeted within four years and production shipments, if they arrive, within the next decade. Yu told the outlet that no standard yet exists for integrating this kind of memory with an accelerator, which means Nagare might have to come up with the interface itself. Datta also mentioned reliability to the outlet, as single-electron effects can shift a cell’s threshold enough to upset the stored bit. It also remains to be seen if the tested three-transistor cells work sufficiently well as a two-transistor, single-shield product.

Even if Nagare clears those hurdles, a more important one lingers: It currently has no fab. The plan to scale depends on getting partners for fabrication as well as packaging. Nagare is reportedly looking for an R&D fab partner so it can scale beyond the university clean room. Perhaps the most similar type of memory-on-compute shipping today, and the one Datta cited to the outlet as a model for working with chipmakers, is AMD’s 3D V-Cache.

Z2RAM isn’t the first capacitorless memory to promise a 5x improvement over SRAM in density; it follows in the footsteps of Innovative Silicon’s Z-RAM from 20 years ago, a technology AMD licensed, though it was not pursued. A Georgia Tech paper due at IEDM in December covers a different device, a one-transistor, one-ferroelectric-transistor cell, aimed at the same gap between SRAM latency and DRAM density.

Gelsinger, previously CEO of Intel, which started as a memory company, phased out Optane, a low-latency non-volatile memory, in favor of CXL. Optane sought to bridge the gap between slower non-volatile storage, such as HDDs and standard SSDs, and DRAM. Now he sits on Nagare’s board, and Playground Global, where he is a general partner, led the startup’s $5 million round as Nagare searches for a solution to a different but related problem.

Nagare declined to share measured retention, latency, or energy figures. The founders’ boosted cell already holds data at 85°C longer than a cache needs, but until a fab-built, multi-layer Z2RAM stack is measured, retention above 95°C included, its headline numbers remain projections.

India wants to develop its own graphics processing unit (GPU) within the next two years as the country steps up efforts to build a domestic semiconductor industry and reduce its dependence on foreign chip suppliers, reports ETGovernment. The target was outlined by S.Krishnan, secretary of India's Ministry of Electronics and Information Technology (MeitY), in a November 4 interview. "Under India Semiconductor Mission 2.0, we intend to target the development of an indigenous GPU chip. We should have a GPU chip of our own. This will not happen overnight. It is a project that will require approximately 24 months, and we intend to work towards that objective," Krishnan said.

The proposed GPU is part of a wider plan to establish an Indian hardware and software ecosystem, with Krishnan describing five layers needed to support AI development. These include: energy, accelerator chips, computing infrastructure and servers, AI models and applications. Indian companies such as VVDN, Kaynes and Avalon are already manufacturing servers, while the Centre for Development of Advanced Computing (C-DAC) has developed its Rudra server range, whose systems are designed to support AI workloads, after which the government transfers the technology to local manufacturers. Krishnan also sees AI as a potential repeat of the opportunity India's IT industry experienced during the Y2K (the year 2000 bug) transition. "AI could create a similar opportunity, although the nature of the work will be different," he said.

The comparison is big for a country whose IT-enabled service sector employs about 6 million people. A NITI Aayog paper estimates that roughly two million existing jobs could become redundant as AI adoption changes the industry, but around 4 million more jobs could emerge. Krishnan argues that Indian companies could benefit from helping businesses worldwide integrate into their AI operations, just as they benefited from the demand for software services around the turn of the century.

The country has already attracted major interest with ASML, partnering with Tata Electronics to equip India's first commercial semiconductor fabrication facility in Dholera, Gujarat. The planned facility is expected to use 300mm wafers and eventually reach a capacity of 50,000 wafers per month. Intel also announced a strategic partnership with Tata Group covering semiconductor manufacturing and packaging for the Indian market. However, the proposed GPU remains an early-stage target. Krishnan did not identify a manufacturer, chip supplier, or builder for the project. India is also looking to bring its own homegrown SHAKTI and VEGA processors to commercial markets. Both are based on the open-source RISC-V architecture, allowing local developers to build processors without relying on proprietary CPU designs. Notably, these are CPU designs, separate from the GPUs now being targeted by MeitY.

That said, it is not the first time India has attempted to build its own GPU production unit. In 2019, India's IT Madras released a software development kit that allowed developers to begin building applications before the processors were commercialized. The project included several processor classes aimed at different markets, from embedded devices and micro-controllers to workstations and server workloads. The effort has continued since then, with the Aries 3.0 development board, which uses the C-DAC’s VEGA ET301 processor, being introduced in 2024. The 32-bit chip runs up to 100MHz and includes 26KB of SRAM and is intended for relatively simple applications such as sensors, wearables, and Internet of Things devices, rather than desktop PCs or graphics-intensive workloads.

However, there are signs that the SHAKTI and VEGA platforms are nodding beyond development boards and into practical applications. At the September 26 SEMICOM India event, the government highlighted projects using the processors, including an autonomous water-cleaning robot around SHAKTI and a digital telescope using VEGA. Another VEGA-based project was designed to monitor forest environments. The government's Design -linked Incentive (DLI) program is already supporting more of that work. MeiyT says 24 companies received assistance under the scheme, and subsequently raised venture capital or other private investment. Their projects include microcontrollers, drone flight controllers, smart meter chips and CCTV cameras.

India's semiconductor market is currently valued at just about $50billion and is expected to approach 100 billion by 2030, according to a report by the India Electronics and Semiconductor Association (IESA). The government wants local companies to capture more of that growth domestically rather than remain dependent on imported components.

Micron has paused construction on its Fab 11E site at Taoyuan as the company and its Taoyuan labor union have failed to reach an agreement regarding clearer profit-sharing terms. Bloomberg reports that activity on the site has all but halted, except for minor safety work, with some sources saying that executives are concerned about uncertainties regarding negotiations with its workers. The company hasn’t released a statement about the move but has already informed local officials about the suspension.

“Taiwan plays an important role in Micron’s global footprint, and our operations today continue as normal,” Micron said. “We are confident in maintaining business continuity for our customers.” The company has recently announced a bonus that could give as much as five times the annual salary of some eligible workers, and has also wrapped up a deal with the bigger Taichung union, although some members say they were dissatisfied with the outcome. On the other hand, the Taoyuan union is still holding out for better terms, with the two parties set to meet again on November 6. It even launched a one-day strike last month to show the chipmaker its resolve and how its operations could be disrupted if it does not meet their demands.

Workers from the big three memory chip manufacturers — Micron, Samsung, and SK hynix — have been protesting recently and demanding a bigger slice of the massive profits that these companies are currently making from the AI memory chip boom. SK hynix has recently agreed to pay staff $50,00 apiece, with each employee set to receive $477,000 in bonuses this year and up to $900,000 next year. Samsung Foundry workers also fought for a $340,000 average bonus, which received approval at the last minute and averted a massive strike that would have disrupted the company’s operations. Employees from these South Korean companies expect to nab performance bonuses of up to $400,000 and are rejecting coveted overseas training programs in favor of cold, hard cash.

While the company hasn’t made a statement regarding the suspension of work on its Taoyuan site, it’s hard to believe that the move happening so close to its next meeting with the Taoyuan union is a coincidence. It should be noted that Micron is also developing other sites across the world, with plans for an HBM fab in Japan, a $24-billion development on the way in Singapore, plus facilities across the U.S. Nevertheless, the company says it is looking forward to reaching an agreement with the workers, with the Taiwan government hoping for a win-win outcome for both parties.

Marvell Technology Inc. has signed a definitive merger agreement to acquire Lumentum for an enterprise value of $115 billion, combining two of the biggest players in the data center optics market into one company. According to a joint press release on November 2nd, Lumentum shareholders will receive 4.5 Marvell shares for each share they own, which the companies put at about $1,132 per share. This figure represents a 23.9% premium over the company's unaffected closing price on October 28, the last trading day before reports of the deal affected prices.

The agreement — which leaves Marvell's current shareholders with about 67% of the combined company and Lumentum's with about 33% — is reportedly the second-largest tech transaction deal ever after the SpaceX-xAI merger, according to Bloomberg. Both boards have approved the deal unanimously, and it is expected to close in the first half of 2028, pending regulatory and shareholder approval.

The acquisition represents another significant expansion of Marvell's optical infrastructure portfolio, following its $10 billion acquisition of Inphi in 2021 and its $3.5 billion upfront purchase of optical interconnect startup Celestial AI, completed in February 2026. All three mergers and acquisitions involved companies handling different parts of one of the most critical AI infrastructures: optical connectivity.

As AI infrastructure continues to scale, optical connectivity is becoming increasingly important for moving vast amounts of data between processors, racks, data centers, and even on the accelerator board itself. With the acquisition of Lumentum, Marvell, which already supplies optical DSPs, silicon photonics, and high-speed SerDes, is positioning itself as one of the industry's major suppliers of optical interconnect technologies, spanning scale-across and scale-out networking to emerging scale-up and scale-in connections.

Why AI infrastructure is moving towards optical connectivity

Modern AI data centers house thousands of interconnected accelerators exchanging enormous volumes of data. As data volume, speed, and travel distance scale, copper interconnects, the conventional medium for inter-rack connections, hit physical limits, becoming impractical at around one to two meters. The industry's solution has been a transition to optics, moving data as light instead of electrical signals.

First, optical transceivers and fiber optics replaced copper for inter-rack connections and beyond. Pluggable transceivers containing a laser chip, digital signal processor (DSP) chips, and several optical components convert the accelerator's electrical signals into light for transmission over fiber, then convert them back into electrical signals at the receiving end.

The industry is also looking to bring optics into the accelerator package itself with co-packaged optics and near-packaged optics. In conventional packages, signals from the logic chip have to travel inches along copper traces across the board to reach the transceiver. Co-packaged optics takes the optical engine out of the pluggable module and places it as a photonic integrated circuit (PIC) chip directly on the switch or accelerator package, shrinking the electrical path.

These shifts to optics have made optical interconnects one of the most critical AI infrastructure markets, driving several multi-billion-dollar deals and major partnerships among industry players across the different technologies and processes involved.

From silicon to lasers: What Marvell and Lumentum bring to the table

The optical interconnects market encompasses several critical technologies. On the electronics side, semiconductor chips such as high-speed serializer / deserializers (SerDes) and optical DSPs prepare and process electrical data signals. Electronics also include analog components such as drivers and transimpedance amplifiers (TIAs) that interface with the optical hardware. Photonic integrated circuits (PICs) use microscopic optical components such as waveguides, modulators, and photodetectors to manipulate light, encode information onto it, and convert received light back into electrical signals, combining all of this into a single chip.

Whether an optical engine sits inside a pluggable transceiver or directly on the board, it still needs a laser, either integrated into the assembly or supplied externally, which brings us to another specialized branch of semiconductor manufacturing: laser technology. Lastly, fiber optic cables and associated passive optical components transmit and distribute light while optical circuit switches redirect optical connections through a network.

Marvell already covers most of the electrical and electronics side, with a portfolio that includes custom AI accelerators, Ethernet switches, high-speed SerDes interfaces, DSPs, optical drivers, TIAs, and silicon photonics. Lumentum, on the other hand, supplies many optical components, including high-performance lasers, modulators, photodetectors, optical transceivers, and optical circuit switches. Combining these portfolios and processes allows Marvell to develop more complete solutions, designing and optimizing electrical and optical components as part of the same system.

Perhaps the most strategically important part of Lumentum's business is its expertise in compound semiconductors, particularly indium phosphide (InP), which is critical for laser and other optical chips. Unlike conventional silicon, which has an indirect bandgap and is inefficient at generating light, InP-based semiconductor structures can efficiently emit and detect light, making the material well suited for manufacturing high-performance lasers and other optical components used in high-speed communication systems.

Lumentum is also bringing its manufacturing experience to the merger. Unlike Marvell's predominantly fabless semiconductor business, Lumentum directly controls its front-end semiconductor fabrication processes, owning and operating specialized InP fabrication facilities, which its CEO Michael Hurlston described as the world's largest InP manufacturing footprint during the acquisition announcement. If the deal closes in 2028, Marvell will transition into a hybrid model, inheriting Lumentum's internal factories while keeping its chip side outsourced. The combined company would also gain access to gallium arsenide (GaAs) technologies.

A $115 billion bet and a long road to 2028

Over the years, Marvell — already one of the biggest custom ASIC suppliers, with clients such as Google, AWS, Meta, and Microsoft — has also strategically positioned itself as a major player in the optical interconnects market, supplying the largest optical transceiver manufacturers. In March 2026, Nvidia invested $2 billion directly in Marvell in a partnership that brings Marvell’s custom XPUs and scale-up networking into Nvidia’s NVLink Fusion ecosystem.

Marvell's biggest optics competitor, Broadcom, also supplies custom AI accelerators, networking silicon, and optical connectivity components, offering both the electronic chips and the optical components. Acquiring Lumentum would give Marvell a more comprehensive portfolio similar to Broadcom's. Nvidia’s separate $2 billion stake in Lumentum would also convert into Marvell shares, consolidating its two $2 billion bets into a single holding.

A key question is how vertical integration affects existing customers, as Marvell supplies optical module manufacturers, while Lumentum sells optical components to companies that also compete with its transceiver business. Merging operations could create concerns among customers that depend on the companies for critical components. Marvell CEO Matt Murphy addressed this issue during the company's November 2 investor conference call, stating that the company intends to maintain its existing component supply model. Lumentum CEO Michael Hurlston also emphasized that supplying competitors is already an established part of the optical industry's business model.

Financially, Marvell expects the combined company’s total addressable market to reach about $550 billion by 2030 — roughly $60 billion more than the two companies’ standalone estimates combined. The companies also expect more than $1 billion in annual run-rate cost synergies, primarily from cost of goods sold. Combining Marvell’s current-quarter guidance with Lumentum’s latest results, the companies put the merged business at about $17.7 billion in annualized revenue.

According to Murphy, pairing Lumentum’s next-quarter guidance with analyst consensus for Marvell’s next quarter lifts that figure to more than $21 billion. Lumentum's recent performance shows the growing demand behind these projections. The company reported $1.26 billion in revenue for its first fiscal quarter of 2027, a 136.5% year-over-year increase. It also announced a second major near-packaged and co-packaged optics design win, which Hurlston said he expects to generate more than $5 billion in revenue.

However, the merger's huge valuation raises questions about whether future growth will justify the acquisition price. Investors reacted negatively to the announcement, with Marvell shares closing down 12.7% at $171.41 on November 2 and Lumentum falling 18.6% to $684.40. For now, the agreement is subject to a lengthy review, with an outside date of November 1, 2027, and options to extend to February 1, May 1, and finally August 1, 2028, if regulatory approvals are still pending. If the deal then fails on regulatory grounds alone, Marvell owes Lumentum $3.2 billion. However, if either board backed out or took a rival offer, Marvell would pay $5.8 billion, and Lumentum $2.9 billion.

Intel Foundry last week made available its Intel 14A process design kit (PDK) version 0.9, an important milestone in the development of this next-generation manufacturing technology. The company says that the production node is reaching performance and yield maturity expected at this stage of development, and the results are backed by silicon validation. Intel plans to release PDK 1.0 in the first quarter of 2027, which will validate the technology's readiness for high-volume manufacturing (HVM).

14A PDK v0.9 is here

A process design kit contains transistor models, design rules, and other information that enables chip designers to develop products for a particular manufacturing process using electronic design automation (EDA) tools. The accuracy and quality of the PDK are crucial for modelling how chips will perform once manufactured, and the release of PDK 0.9 is particularly important because it provides customers with a representation of Intel 14A based on actual silicon measurements rather than on theoretical models or simulations. At this stage, customers can proceed with product development with greater confidence that the technology will meet their requirements when it comes to performance and power consumption.

Intel says that PDK 0.9 lets customers develop designs intended to enter risk production around the time the process is certified, which — provided that PDK accurately reflects the characteristics of manufactured silicon — in many cases enables chip developers to greatly reduce the number of silicon revisions between initial tapeout and mass production. Of course, availability of PDK 0.9 does not indicate that Intel 14A is ready or even close to mass production, as the company expects to validate HVM readiness only with PDK 1.0, sometime in Q1 2027. Again, this does not mean that 14A will enter mass production in early 2027, as Intel itself expects to begin mass production using its 14A process technology in 2028, following risk production for its own products in the second half of 2027.

"From a customer perspective, the PDK 0.9 gives customers the confidence to design products on Intel 14A, as the technology is reaching the industry-standard performance and yield maturity expected at this stage of development, supported by silicon-backed validation," said Ben Sell, corporate vice president and general manager of front-end technology development at Intel Foundry.

Building on top of 18A

Intel 14A builds on top of architectural foundations introduced with Intel 18A but incorporates several substantial enhancements. These include 2^nd Generation RibbonFET 2 gate-all-around (GAA) transistors, PowerDirect backside power delivery (which delivers power right to the transistor source/drain regions without using intermediate connections like TSVs used by PowerVia), and Turbo Cells (high-performance standard cells designed to accelerate timing-critical paths in CPUs and GPUs), which provide chip designers with additional ways to increase performance and optimize power efficiency. Since Intel has previously outlined advantages of these technologies, the latest announcement does not provide updates regarding transistor performance, power consumption, or transistor density figures for Intel 14A.

Beyond improvements to transistor, power delivery, and interconnect technologies, Intel is applying manufacturing experience gained during 12 months of Intel 18A production to accelerate maturation of 14A. Specifically, the company says it has increased investments in inline defect detection, modeling, and simulation to identify potential manufacturing problems earlier in the development cycle. These initiatives are intended to improve manufacturing yields, process variability, ultimately transistor performance, and reduce production cycle times. Intel also says it has introduced several strategic initiatives to accelerate technology development, although it does not quantify their impact.

New collaboration model

Another important change concerns Intel's relationships with equipment and materials suppliers. The company says it has revised its collaboration model to involve technology development teams and external suppliers earlier in the process development cycle. The goal of such close collaborations is to address manufacturing defects and improve equipment capabilities before they become obstacles for yield improvements after the technology enters mass production. Intel also conducts regular yield summit meetings with suppliers to accelerate progress on critical development objectives.

"This has required evolving our collaboration model with equipment and material suppliers, and earlier engagement from our [technology development] leaders with suppliers to drive improvements in defects and equipment capabilities," Sell said.

A bonus of such early collaboration is that equipment and materials suppliers may incorporate Intel's requirements into their standard products and development roadmaps. This could give Intel an advantage over competitors, which would have to either adapt their manufacturing processes to equipment optimized around Intel's requirements or work with suppliers to develop alternative solutions from scratch.

Historically, Intel frequently set the direction for semiconductor manufacturing technologies as other chipmakers subsequently adopted similar approaches. One notable exception was immersion DUV lithography, which Intel adopted after TSMC, which led the development of immersion DUV lithography. By engaging equipment and materials suppliers earlier, Intel could regain some of its historical influence over the development of industry-standard manufacturing solutions, though the importance of this should not be overestimated.

Expanding design ecosystem

Meanwhile, Intel continues to expand the design ecosystem for its 14A technology. Cadence and Intel have established a design-technology co-optimization (DTCO) collaboration focused on next-generation AI-driven design tools and intellectual property, whereas Keysight, Siemens, and Synopsys have announced design-tool certifications for the process. Intel is also working with other software developers and IP providers to validate design flows and reusable building blocks required by prospective foundry customers.

Intel says it is encouraged by customer feedback regarding the progress of 14A development. However, the company has not identified any customers that have committed to manufacturing products using the technology, disclosed customer tape-outs, or announced specific manufacturing agreements, which is normal for the foundry industry. For Intel Foundry, attracting external customers remains particularly important because development costs of modern leading-edge process technologies can only be recoupled when they are used to make hundreds of millions of chips, way more than Intel sells these days. Meanwhile, the commercial success of Intel Foundry with advanced manufacturing technologies depends not only on transistor performance and manufacturing yields, but also on its ability to deliver predictable development schedules.

Looking ahead, Intel intends to continue improving performance, yields, variability, and manufacturing cycle times of 14A, though for now the company does not disclose any actual goals. Intel also plans additional process enhancements and performance refinements for 14A-E and 14A-P nodes after the initial technology becomes available. However, exact schedules for these nodes are not known at the moment.

"Our next major milestone is the Intel 14A PDK 1.0, expected in the first quarter of 2027," said Ali Farhang, corporate vice president and general manager of Intel Foundry's design technology platform organization. "I am looking forward to sustaining this level of quality across future releases and continuing to earn our customers' trust by delivering on our commitments with a customer-first mindset."

A memory smuggler has detailed how he gets export-controlled HBM chips from South Korea into China using a loophole. According to The Information, the smuggler owns a chip design firm that build cheap, low-performing processors that fall under the U.S. and South Korea’s export controls. They are then paired with expensive HBM from Samsung and SK hynix, that, on their own, are banned for export to China. But because export control rules only look at the performance of the server processor and not at the other components attached to it, this allows the HBM chips attached inside them to slip under the radar and make their way into China.

It’s not a risk-free operation, though. Once the mediocre processors with high-end memory chips land in Hong Kong and are smuggled across the border into Shenzhen in the luggage of commuters that cross between the two regions daily, they end up in workshops where technicians heat up the boards to soften the solder, gingerly lift the crucial memory chips, and discard the rest of the components. Despite having a high failure rate, the high price of HBM chips makes the procedure quite lucrative.

A Shenzhen-based chip broker has been making big money matching up suppliers such as the smuggler and companies that are desperate for HBM. “A year ago, a single HBM3E unit changed hands in China for several hundred dollars,” he tells the publication. “Today it’s about $4,000.” With an AI chip requiring six to eight high-end memory chips, that means the broker is raking in $24,000 to $32,000 for every AI GPU.

Chinese AI labs face this exact memory chip bottleneck when acquiring AI GPUs. While Chinese memory manufacturer CXMT has already begun risk production of HBM3E and is expected to mass produce them by the end of this year, it’s still reportedly suffering from low yield, which makes their chips expensive to produce and procure. We see this with Huawei’s Ascend 950DT, its current top-of-the-line processor that goes for about $37,000 — it offers similar pricing to Nvidia’s B200 AI GPU but only delivers half the performance of the previous-generation H100.

Huawei has reportedly said that its next-generation flagship AI processor, the 960DT, would deliver a similar performance as the H100. However, since the company cannot purchase HBM from Samsung and SK hynix, and Chinese memory manufacturers do not have the capacity to supply all its chip demands, Huawei told customers that they have to find the HBM that these servers need themselves. This would further fuel the demand for these chips, increase the price and make it more lucrative for smugglers to set up similar operations.

But given that this method of moving HBM chips into China is becoming more popular, the smuggler fears that South Korean and U.S. authorities would clamp down on their operations soon. Washington has been going down hard on activities like this, and we’ve seen high-profile arrests including some Super Micro executives and the CEO of a California-based tech company. Other countries like Taiwan and Malaysia have been ramping up their anti-smuggling activities, too, so it’s probably just a matter of time before Seoul follows suit.

Some 700 Micron employees in Taiwan will receive five years’ worth of salary in bonuses as the company announced three bonuses in a single payout. According to Digitimes, this accounts for about 17% of the over 4,300 production-line employees working at Micron Taiwan. The remaining staff will not come out empty-handed, though, as they will receive three bonuses in the month of October. The news comes as Micron continues to battle worker unrest and unions fighting for increased pay.

The lump-sum payout consists of three incentives — an annual performance bonus that’s estimated to be between 7.5 and 12.5 months of salary for the majority of workers, a mass-production bonus amounting to 20% of their annual salary, plus a one-time $31,000 (NT$1,000,000) appreciation bonus which will be prorated for employees who haven’t reached a full year of service. Micron workers across the globe also expect a new quarterly profit bonus which will be paid 50% in cash and 50% in stock. This bonus will start in January 2027, with the first one to be paid 100% in cash.

Micron is following in the footsteps of Samsung and SK hynix, which have recently paid out massive bonuses to their workers of up to $400,000. This is a direct effect of the AI-driven memory chip boom, which saw the big three memory chip manufacturers — Micron, Samsung, and SK hynix — raking in massive orders from AI hyperscalers. The record profits that these companies are drawing from the appetite for AI data centers have led workers on production lines to demand a slice of the pie. Samsung workers voted to accept a $340,000 average bonus in May 2026, while SK hynix workers are set to receive $477,000 in bonuses this year, which could potentially grow to almost $900,000 in 2027.

Despite this seemingly massive payout, the workers’ union at Micron Taoyuan is still in the midst of a dispute with management regarding their pay. Some officials of the group have already launched a one-day strike as they call for clearer profit-sharing arrangements and terms for bonuses, with nearly 70% of members at the Taoyuan site turning down management’s latest offer. The two sides are tentatively set to meet on November 6 again for further negotiations. On the other hand, the union at Micron Taichung has already agreed to a 10% employer’s contribution towards worker pensions and a tripling of their day-shift allowance.

These bonuses allow workers to get a share of the massive profits that the chipmakers are raking in at the moment, allowing them to stay competitive for chip talent. However, their reliance on performance and profit bonuses also means that these incentives could fall precipitously if AI demand falls and the demand cycle returns to normal.

HP, Asus, and Acer have reportedly moved some of their manufacturing capacity back into China as increasing component costs — driven by AI — bite into their margins. According to Nikkei Asia, increasing bill-of-materials costs have made China’s experienced workforce, relatively lower prices, and established supply chain ecosystem a more attractive option. However, they are not going back to traditional suppliers like Foxconn, who have focused their production capacity on AI data centers. Instead, they’re signing contracts with smaller Chinese contract manufacturers, like Luxshare, Huaqin Technology, and Longcheer Technology, that are trying to establish themselves in PC manufacturing.

Many PC brands slowly moved out of China in 2024 and 2025 as the U.S.’s sanctions and tariffs on China have increased prices and forced them to find friendlier nations. While these nations do not have established supply chains and expertise like China, it at least spreads the risk as manufacturers avoid getting caught up in geopolitical tensions.

However, it seems that rising component prices have forced them to move back some of their capacity into China. The biggest culprit is the AI-induced memory and storage chip shortage, which has caused memory prices to climb an unprecedented 500% in 12 months. More than that, other parts like PCBs and fiberglass cloth used in motherboard manufacturing are seeing increasing prices, which Acer chairperson and CEO Jason Chen bemoaned as suppliers hyping shortage fears to protect margins.

While tech companies aren’t abandoning their “China+1” diversification strategy, the mature industry in China is helping offset increased component costs. Aside from that, the Chinese contract manufacturers often have better access to memory chips from domestic manufacturers like CXMT. "These Chinese contract manufacturers have been telling potential clients and computer makers that working with them could be a good option for securing better access to Chinese-made memory chips," a supply chain manager in the computer ecosystem told Nikkei Asia. "They are marketing themselves as a good alternative to even help sort out the supply chain."

Moving back some manufacturing capacity into China is easing some of PC manufacturers’ cost concerns, but it’s also negatively impacting the newly established supply chains in Southeast Asia. "We built two new production lines in Thailand for the PC clients, and now they are moving substantial orders back to China,” one manager at a PC component supplier told the publication. “Those two lines have not yet turned profitable, and I don't know when they will add the orders back."

Unfortunately, building an entire supply chain for PC manufacturing is slow and expensive. The U.S. has been trying to accomplish this for years, and, so far, only Anduril has attempted to build laptops with 90% of its component costs coming from the U.S. and other allied countries. Even then, it expects its devices to be around 20% more expensive than the competition, which it could afford by offering them mostly to critical industries that demand supply chain security, like the government and the military. But if you’re a PC manufacturer vying for customers in the consumer market, you’re likely incentivized to find the lowest possible costs to be able to compete in pricing.

Solidigm, an American subsidiary of SK hynix, one of the biggest flash chip makers on the planet, is reportedly in talks with the Commerce Department over plans to invest $45 billion in a new plant to be built in the United States. But, Bloomberg reports, there's a catch — Solidigm wants to be given the go-ahead to export equipment to upgrade its existing plant in Dalian, China. The company has purportedly told officials that the upgrades would allow the Chinese plant to then help finance the cost of its U.S.-based counterpart, according to unnamed sources. It's as-yet unclear how the proposal was received, or whether the Commerce Department is inclined to agree to the deal.

The U.S. government has been keen to drive at-home manufacturing wherever possible, including for chips used in its computers and data centers. National security is regularly cited as a key reason behind the move. It's also the reason for the government's stance on exporting technologies to China, including the equipment that Solidigm says will help upgrade its Dalian plant. Similar export restrictions are in place for high-end AI data center components, with a black market having sprung up to take the place of sanctioned sales. Earlier this month, it was reported that some of Nvidia's powerful Blackwell Ultra B300 GPUs are being used in China Telecom data centers, with no explanation of how they got there. A 2025 report claimed that a cool $1 billion worth of Nvidia AI chips had been smuggled into China, a figure that is sure to have increased significantly as 2026 draws to a close.

In this case, Solidigm's planned Chinese factory upgrades could be mutually beneficial, allowing funds to be transferred to the new U.S. plant. But that requires the U.S. government to give it permission to ship the machinery in the first place, something that is far from guaranteed. The Dalian factory produces NAND flash memory, the likes of which are used in everything from relatively simple devices to full-blown data centers. It also comes at a time when global NAND production is a hot-button topic. Samsung and SK hynix are upgrading their Chinese factories to produce more of the chips used in AI data centers in an attempt to meet growing demand. Manufacturers have already slashed production of consumer-focused memory in favor of the more lucrative data center-grade components, causing prices to spike globally. This volatility in the market as a whole was given as one of the reasons SK hynix chose to cancel a planned Solidigm IPO earlier this week.

Beyond dangling a $45 billion plant, Solidigm has also allegedly told the Commerce Department that its total investment in U.S. manufacturing could reach $100 billion eventually, with construction in New York penciled in for 2027. The company is fresh from its latest earnings call, where it announced revenues of $75 billion with $60 billion in operating profit, and $28 billion in net. The company made no mention of its Dalian plant or a planned US investment, but did warn that memory shortages are set to last through 2030.

TSMC is weighing raising prices for its Chip on Wafer on Substrate (CoWoS) advanced packaging technology by as much as 20%, reports Trendforce, citing supply chain sources and local media. The increase reflects strained capacity amid AI demand and longer delivery times for chipmaking tools. Such a hike would be significant, as CoWoS is already one of the tightest links in the AI supply chain. TSMC has yet to confirm the report.

CoWoS combines logic dies and high-bandwidth memory (HBM) stacks within a single package, which is how AI accelerators get the data bandwidth that demanding workloads require. Building these packages is only getting harder as chip designers cram in more compute and memory. Nvidia’s Blackwell already pairs two large GPU dies with eight HBM3E stacks, whereas the upcoming Rubin and Rubin Ultra are expected to push integration further, which will increase pressure on packaging and the supply chain that supports it.

Testing is turning into another bottleneck. Blackwell reportedly takes three to four times longer to test than Nvidia’s previous-generation Hopper, and Rubin could need as much as seven times longer. Extended test cycles keep equipment occupied for longer, which makes it harder to increase output as demand grows. GPUs are not the only products competing for capacity either, as server CPUs and custom ASICs also need advanced packaging, adding more strain to an already crowded supply chain.

Tools are also taking longer to arrive, as equipment lead times have reportedly stretched from three to six months to as long as eight months, making timely access to fab equipment increasingly important. As a result, TSMC has reportedly placed this year’s equipment orders at existing prices instead of negotiating discounts or extra features — a departure from its customary approach of using its purchasing power to secure better terms. Essentially, getting the tools on time now appears to matter more to the company than getting them cheaply.

The squeeze echoes a report from September, which said that TSMC’s projected semiconductor equipment requirements had almost doubled in six months as the company expanded production to meet AI demand. Cliff Hou, deputy co-COO at TSMC, said that by July the company’s expected equipment needs had reached 1.9 times its original estimate as AI demand accelerated. “Compared with the pattern 30 years ago, we have never seen the demand increase that much, that frequency of changes,” Hou said at the time.

TSMC is also trying to broaden its packaging supply chain. Earlier this month, GlobalFoundries agreed to produce silicon interposers for TSMC’s CoWoS in the U.S. under a five-year contract worth $2 billion, with production expected to ramp up in the first half of 2028. However, interposers are only one part of the packaging flow, so the agreement alone will not eliminate shortages.

Higher costs are not limited to packaging. TSMC is reportedly considering broader price increases for 2027, with wafer prices on advanced process technologies expected to rise by 5% to 10%. Customers using 2nm and 3nm-class nodes could face the steepest hikes, whereas those seeking capacity beyond their original allocations may have to pay additional premiums, which could push some costs up by as much as 25%.

Industry estimates cited by Trendforce put TSMC’s monthly capacity at over 106,000 wafers in 2026, with a target of 227,000 wafers in 2027 as the company works to keep pace with demand for increasingly complex AI processors. If both the packaging and wafer price increases materialize, the cost of AI hardware will likely climb further, and some of that will inevitably be passed down the chain.

On October 21, during GTC Berlin, Nvidia announced several massive, multi-billion-dollar deals with supply chain partners across substrates, advanced packaging, semiconductor testing, and optical engines to expand production capacity. Aimed at overcoming severe bottlenecks restricting the current and future AI infrastructure buildouts, the deals feature commitments and production roadmaps stretching through 2028, securing capacity for Nvidia and ensuring resiliency and redundancy in its AI accelerator supply chain. “We are in the midst of the largest infrastructure buildout in human history. Demand is extraordinary. Capacity is the constraint,” said Nvidia CEO Jensen Huang. “Our supply chain partners are the world’s best manufacturers. I’m grateful they are expanding capacity around the globe to scale production and help us deliver the AI supercomputing systems powering this new industrial revolution.”

The deals cover two major AI accelerator supply chain categories: hardware interconnects and OSAT (Outsourced Semiconductor Assembly and Test). Under hardware interconnects, Nvidia is securing capacity for both substrates and co-packaged optics. Nvidia has signed deals with Ibiden, Unimicron, and Samsung Electro-Mechanics — three of the world's five largest substrate manufacturers — to support its production capacity expansion and reserve significant portions of that capacity for the chipmaker. The company says it plans to secure 2.5x dedicated substrate capacity over the next three years. Nvidia has also signed agreements with SPIL (Siliconware Precision Industries Co., Ltd) to expand manufacturing capacity for the optical engines used in co-packaged optics by 15x by mid-2027.

On the OSAT side, Nvidia and Amkor are targeting a 300% increase in interposer wafer capacity by the end of 2028 through expanded advanced packaging capacity in South Korea, to support higher production volumes for Nvidia's platform. The company also plans to double its semiconductor testing capacity by 2027, investing $1.1 billion to reserve capacity from KYEC (King Yuan Electronics Co., Ltd.), the world's largest semiconductor testing company, which currently handles nearly all of Nvidia's chip testing.

Nvidia currently leads the AI chip market by a considerable margin, with its extremely powerful accelerators sitting in a vast majority of AI data centers globally. These deals target major bottlenecks in the AI chip supply chain, suggesting Nvidia doesn't plan to relinquish its position soon. So, why these specific deals? What are the exact details? What's the broader play? And where do Nvidia's competitors and the rest of the AI industry stand?

Uncorking bottlenecks

The substrate base, a specialized intermediary layer in every accelerator package that connects the tiny silicon chips above it to the board below, is one of the most critical bottlenecks in the AI chip supply chain. As we detailed in our comprehensive substrates roadmap, this indispensable physical layer, manufactured by only a handful of companies, is expanding in both the X-Y and Z axes as chip makers package an increasing number of components onto one board. Nvidia's Blackwell generation places two reticle-sized GPU dies and eight HBM3E stacks on a single package. Its Rubin and Rubin Ultra architectures mount even more components. As a result, each substrate now consumes much more material and production capacity, even as demand for individual substrates soars.

Fubon Research estimates that Nvidia would supply around 12.4 million data-center AI GPUs in 2028, up from a projected 8.2 million in 2026. Each one would feature a substrate layer. Nvidia is staying ahead of the curve, with a planned 2.5x capacity expansion over the next three years, led by Ibiden. Earlier this year, the company signed a deal to provide a multibillion-dollar capacity reservation advance to support Ibiden's Ono Plant in Japan, targeting 3x the plant’s current individual capacity.

To reach its 2.5x target, Nvidia has also brought on Samsung Electro-Mechanics, Samsung's substrate-manufacturing subsidiary, as a supplier. Beyond the immediate capacity from Samsung Electro-Mechanics’ existing operations, the deal will support facility upgrades and new plants in Busan and Sejong. Nvidia is projected to account for a significant portion of the substrate manufacturer’s output by 2028. To build even more redundancy, Nvidia also signed a capacity reservation agreement with Unimicron, supporting the latter's substrate manufacturing expansion in Taiwan. The expansion will reach full capacity by mid-2028 but is expected to start providing capacity by Q2 2027.

Next on Nvidia's to-expand-capacity list announced on October 21 is co-packaged optics. As next-generation speeds surpass 224 Gbps per lane, traditional copper traces on the board consume considerable power to move data even a few inches from the processor to the edge of the board. To address this, the industry is moving the optical engine into the accelerator package itself via co-packaged optics. Nvidia had long detailed its plans for silicon photonics and co-packaged optics as the standard for future AI accelerator packages. The company has signed a deal with Taiwanese optical engine manufacturer SPIL to expand production capacity by 1,400% by mid-2027, with plans to double again by the end of 2028.

A 4x increase in packaging, double the testing, and $1.1 billion specifically for U.S. facilities

Interestingly, the world's biggest semiconductor company, Nvidia, doesn't own a single Fab. After TSMC manufactures the logic chip and binds it with memory chips on a silicon interposer, final-assembly companies such as Amkor package that integrated module with the substrate and protective casing into the final accelerator package. These final steps are increasingly incorporating co-packaged photonics chips. Nvidia’s deal with Amkor aims to expand the latter's interposer wafer capacity by more than 300% by the end of 2028, through advanced packaging capacity expansions in South Korea. Amkor confirmed the deal is worth $1.3 billion, bringing Nvidia's total investment in Amkor across its Arizona and South Korea facilities to $3 billion.

After final assembly, finished Nvidia AI accelerator packages are shipped to KYEC for extreme testing. KYEC currently handles nearly all of Nvidia's chip testing. It therefore comes as no surprise that Nvidia expects semiconductor testing capacity to double from calendar 2026 to 2027 through buildouts across KYEC’s facilities in the U.S., Taiwan, and Singapore. On October 13, Nvidia signed a deal to pay KYEC $1.1 billion to reserve testing capacity at KYEC's new $1.4 billion U.S. facility, where high-volume production is slated to begin in April 2027. The funds will build domestic testing capacity and bolster the domestic supply chain. At the same time, KYEC is aggressively expanding operations in Singapore, where it expects high-volume production to begin in February 2027.

The bigger picture

Nvidia has been aggressively securing production capacity and long-term supply commitments to meet anticipated demand for its next-generation AI accelerators. According to its August 2026 financial disclosures, the company had accumulated $279 billion in outstanding supply and manufacturing-capacity commitments by July 2026. The company has since signed several additional deals. These commitments cover future component purchases and manufacturing capacity reservations, particularly for memory and chip production. Combined with its more recent agreements, Nvidia is securing nearly every stage of its AI accelerator supply chain, from semiconductor fabrication and HBM memory to substrates, advanced packaging, optical interconnects, final assembly, and testing.

Of course, the rest of the industry isn't standing by. On May 21, 2026, AMD announced over $10 billion in investments across Taiwan's semiconductor ecosystem, specifically targeting advanced packaging and manufacturing partnerships. On October 6, CEO Lisa Su confirmed that AMD intends to increase those investments further. The company is working with TSMC, packaging partners, substrate manufacturers, and memory suppliers to increase production substantially in 2027. Google and Amazon are also aggressively expanding their custom TPU and Trainium accelerator programs.

Intel, meanwhile, is positioning its foundry and advanced packaging operations as alternatives to TSMC's increasingly constrained production capacity. The company is expanding its EMIB-T packaging technology, with reports indicating that Google has already reserved Intel capacity to package more than three million TPUs in 2028. Intel is also advancing its 18A and 14A manufacturing processes as it attempts to attract major external customers.

Samsung is expanding its semiconductor operations as well. The Korean company, which held approximately 5.9% of the global foundry market by revenue in Q2 2026, is ramping up its 2nm manufacturing technology and preparing its Taylor, Texas, facility for volume production in 2027. As detailed in our comprehensive Samsung foundry roadmap, the company is investing heavily in its manufacturing operations as it attempts to close the considerable gap with TSMC.

Perhaps the most ambitious player is new entrant Elon Musk's Terafab, a joint semiconductor manufacturing project involving Tesla, SpaceX, and xAI. The project aims to eventually manufacture the equivalent of one terawatt of AI computing capacity annually, an extraordinarily ambitious target given the industry's current scale. Intel joined the project in April, and Musk later confirmed plans to use the company's 14A fabrication technology. The project aims to deliver its first experimental chips in 2027 and begin high-volume production by the third or fourth quarter of 2028.

Nvidia and other semiconductor firms are continuously fighting against emerging bottlenecks, but compute doesn't come online overnight, and fabs aren't built in a day. So, while almost every inch of the semiconductor supply chain remains constrained, it remains likely that big-name players will continue to invest heavily to ensure that products continue to flow into neoclouds and data centers alike.

Cadence, one of the largest electronic design automation (EDA) companies, has unveiled Maestro, its new portfolio of domain-specialized AI models tailored for its chip design agents, in a press release sent just ahead of earnings. In initial results compared with general-purpose AI models, Cadence claims up to a 30% improvement in the quality of results and that Maestro effectively uses fewer tokens for the same task, with up to 5x the token efficiency. The first models “are available to select early access customers” in Q4 2026, and customers may run them on Cadence’s cloud, public clouds, or customer-controlled on-premises environments and post-train them on their own “proprietary data, designs, and workflows.” To learn more about Maestro, we spoke with two Cadence executives: Rob Knoth, senior group director of strategy and new ventures, and Paul Cunningham, senior vice president and general manager.

This approach is distinct from Synopsys’ own specialized model, GPT-Synopsys, which will run on OpenAI-hosted infrastructure, without using customer data to train the model. The models of both EDA giants, announced less than a month apart, now split on where a customer’s design data goes. Where they might not differ is why: Paul Cunningham, senior vice president and general manager at Cadence, told Tom’s Hardware Premium that agent costs have “really started to explode,” adding, “And I think the world realized so.” That makes it a natural step, he said, to move more of the agents’ iterating “into the weights of the models themselves.”

Maestro takes this step through Cadence’s AI Super Agents, which “interpret design intent, decompose tasks” and “orchestrate the Maestro portfolio with other leading frontier and open-weight models,” evaluating trade-offs to guide decisions with domain expertise. It also uses reinforcement learning (RL), where Cadence’s “deterministic solvers evaluate outputs against engineering objectives, constraints and ground truth,” and, importantly, the results feed back into the models for improvement.

The models include Nvidia’s Nemotron, and customers can run the customer-data training step themselves with Cadence’s fine-tuning harness, potentially “on their own GPUs, on their own network,” Cunningham said. He added that Nemotron, specifically, was “giving really solid results and actually improving very, very fast.”

One constant that keeps popping up with agentic EDA is the need to nail down what the numbers actually measure. In chip design, quality of results usually refers to the design’s power, performance, and area, though Cadence didn’t specify what its 30% figure measures. Both it and the 5x token efficiency figure are measured against “a general-purpose foundation model,” which Cadence told us is the open-source model Maestro started from before its training. The company wouldn’t name the foundational AI model that Maestro is derived from beyond mentioning that it is “one of the leading open source models that’s very competitive with commercial frontier models.”

Cadence credits the token savings to balancing its EDA and system design automation (SDA) “tool calls with LLM invocations.” As an analogy, Cunningham said, “You don’t need to drive to Safeway in the jet engine,” and you want to use “the right model at the right time for the right task.”

Runtime does matter, too: as Rob Knoth, senior group director of strategy and new ventures at Cadence, told Tom’s Hardware Premium in September that a tool call could take anywhere from hours to days to return a value, while the AI industry’s training loops are “used to minutes.” Efficiency could also lower costs, since Maestro use counts toward Cadence’s agent pricing, a subscription with a consumption allowance and charges for use beyond it, Cunningham said. He didn’t say whether the token savings cut a customer’s bill.

Being flexible for the customer is a key element of any solution, and for Cadence’s competitor Synopsys, this lies in Autopilot, which Synopsys says allows customers to “choose among commercial, open-source, and fine-tuned language models” across “Synopsys-managed and customer-managed deployments,” with cloud or on-premises infrastructure. For agent security, such as sandboxing, Cadence says it’s working with Nvidia on an integration with Nvidia’s OpenShell Reference Architecture, which Nvidia launched last week, naming both Cadence and Synopsys. These options can help protect customer intellectual property.

Cadence has had a busy 12 months with customers and agents alike. During Cadence’s July earnings call, CEO Anirudh Devgan said ChipStack, its design and verification agent, “has more than 20 customer engagements,” and ViraStack, its custom and analog agent, “more than 25 customer engagements.” Socionext said just last week that it was applying InnoStack. Silicon Labs has also credited ChipStack with accelerating debugging, and both companies say they are watching Maestro next.

Cadence's agentic consolidation began with its acquisition of ChipStack back in November 2025. In June 2026, the company claimed that its agent had reached Level 5 autonomy, which we explored in detail. In September, Knoth teased Maestro’s ingredients to Tom's Hardware Premium a month early, two days before the GPT-Synopsys announcement: “reinforcement learning loops, domain-specific post-training of open-weight models, model routing.” Maestro is now sitting under all four super agents, targeting a similar year-end window to Synopsys’ Autopilot; the table below has the full timeline.

This rapid pace of progress means that a clear distinction has to be made between early access and general availability. Both Cadence and Synopsys can point to customer engagements, and, at least in the latter’s case for the AgentEngineer portfolio and Autopilot platform, general availability remains a goal by year’s end; Cadence hasn’t given a general availability date for Maestro. For GPT-Synopsys, though, only “early technology engagements are underway,” according to its partners. The platforms and agents remain works in progress.

For Maestro, Cunningham hopes for “more case studies, more quantifiable benefits” through Q4. The real story, as he aptly put it, is that “we’re going to bring agents and agentic AI natively into our vertical, not that our vertical is going to get embedded into general-purpose agents.” Only customer results on real workflows will test Cadence’s 30% number, but going by what both companies have shown so far, their own early figures are extremely promising and exciting for the EDA industry.

Intel and AMD have spent decades competing for the processors inside PCs and data centers, but the rivalry hasn't stopped the two companies from working together when their interests align. And now, Intel CEO Lip-Bu Tan has reportedly discussed potential areas of cooperation with AMD chief Lisa Su, adding another possible partnership to the mix as Intel tries to regain its footing in the semiconductor industry.

According to a recording (embedded below) of Tan’s October 24 fireside chat with Chinese American Semiconductor Professional Association (CASPA) President Jimmy Cheng, the Intel CEO outlined his plans to rebuild the company’s CPU business, develop chips tailored to specific customer workloads, and attract more customers to its foundry operations. However, Tan did not publicly detail the reported areas of potential cooperation with AMD CEO Lisa Su.

Intel has traditionally built its business around its own processor roadmaps, but Tan says the company needs to be more flexible as customers look for silicon designed for particular workloads. He pointed to Intel's Xeon processors as one area where that approach is changing, alongside continued development of GPUs and accelerators.

"We have to reclaim the leadership in CPU. That is something that I am very determined to do." Tan said.

He also described a change in how Intel approaches customization. "Intel is so proud they never want to modify for customer needs," he said. "I'm modifying it for customer needs, and so that, I think, to me, is a fast-growing area, and I'm double, triple down on it."

The strategy extends beyond conventional CPUs, with Tan identifying application-specific integrated circuits (ASICs), co-packaged optics (CPO), physical AI, and advanced packaging as potential growth businesses. He wants two or three of these areas to eventually contribute around 10% of Intel's revenue each.

Intel's foundry business is another major part of Tan's plans. He said the company's 18A manufacturing process had reached volume production, while development of its next-generation 14A process was progressing strongly. Intel has already released version 0.5 of the 14A process design kit (PDK), which provides chip designers with the technical information and tools needed to develop products for the process.

Tan said version 0.9 was coming next, followed by version 1.0 for volume production in early 2027. "We have multiple customers [who] really want us to really scale their business," he said, referring to interest in Intel's foundry services.

However, Intel did not identify those customers or disclose the size of any potential manufacturing orders during the discussion. Notably, in January, Intel had two prospective customers evaluating 14A test chips, with firm supplier decisions expected during the second half of 2026 and the first half of 2027. Tan also described foundry manufacturing as a business where trust matters as much as technology. Customers hand over wafers that will eventually become products on which their own revenue depends, making missed deadlines or manufacturing problems costly. "The moment we take on the foundry, take on the wafer is a lot of responsibility to make them successful," he said.

He recalled one customer who had waited six to eight months hoping he would become CEO before presenting 15 areas where Intel had fallen short. Tan said he addressed the problems individually, after which the customer agreed to deepen its relationship with Intel.

That said, the prospect of further cooperation would not be entirely new. In October 2024, Intel and AMD established the x86 Ecosystem Advisory Group alongside other technology companies to coordinate improvements to the x86 instruction set architecture and make it easier for hardware and software developers to support both companies' processors.

That cooperation has since moved into AI software. Last week, it emerged that AMD was integrating its ZenDNN optimizations into Intel's open-source oneDNN library, bringing the companies' CPU optimization work for PyTorch AI inference under a common software path. The companies have also worked together on Advanced Matrix Extensions and other x86 capabilities through the advisory group, showing that they cooperate on shared technologies while continuing to compete for customers. For now, however, neither company has announced a new agreement arising from the discussions.

Export controls have kept ASML's most advanced EUV lithography machines out of China. Instead, the country's chipmaking industry has relied on less-capable deep ultraviolet (DUV) lithography machines. By using multiple exposures on critical chip layers, these older machines are still capable of producing performant silicon. However, as multiple patterns are applied there are more chances for defects, longer manufacturing times, and higher bills. We spoke to experts like Chris Mack, co-founder and CTO of semiconductor firm Fractilia, to find out how much further DUV can go.

For years, extreme ultraviolet (EUV) lithography has been seen as China’s biggest choke point in the country’s attempts to build cutting-edge chips. The machines, made exclusively by Dutch manufacturer ASML, use 13.5nm-wavelength light to print some of the most intricate features found on modern processors. Sales of ASML’s EUV systems are subject to export restrictions, forcing Chinese manufacturers to squeeze ever more out of older deep ultraviolet, or DUV, lithography instead. The EUV gap alone between China and the West is at least half a decade, according to some analysts.

But even without access to EUV machines, China has gotten surprisingly far in recreating what it offers through existing technology.

Teardowns of Huawei’s Mate 60 Pro in 2023 found the phone’s Kirin 9000S processor had been made by SMIC using a second-generation 7nm-class manufacturing process without EUV. More recently, analysis of Huawei’s Kirin 9030 found SMIC had pushed its DUV-based process closer still to the density associated with 5nm manufacturing – although it continued to lag behind the leading processes used by TSMC and Samsung.

Multiple patterning

The trick is multiple patterning. Rather than trying to print an overly intricate chip layer in a single pass, Chinese manufacturers are dividing up the complex design into several simpler patterns. Repeat the process enough times and you can etch up something approximating the proper layer you intended.

The trick works. But according to lithography expert Chris Mack, co-founder and CTO of Fractilia, asking whether a chip can be made without EUV overlooks the trade-offs manufacturers make in order to do it.

“When this transition first began, what everyone in the industry said as conventional wisdom is that cost-wise, three exposures on a 193 immersion tool cost about the same as one exposure on an EUV tool,” Mack said in an interview with Tom’s Hardware Premium. “At three, it was about even,” Mack explained. “But as soon as you hit four masks – 193 masks being replaced by one EUV mask – then EUV became more cost-effective.”

It’s also likely to produce a higher quality product with fewer defects. Each time a wafer is patterned, that new pattern has to line up perfectly with everything that’s already been etched beneath it. The more individual exposures needed to produce a single layer, the more opportunities there are for things to go wrong. “If you have, say, four 193 masks, you've got all those different overlays, and you've got all these different process variations that start to accumulate,” Mack said.

Chip designers can try and avoid that by leaving more space around features so the finished processor can actually be manufactured reliably. But that means the chip ends up bigger – and bigger chips become expensive very quickly. Making each die larger means fewer fit on every wafer, and wafers cost a lot of money – tens of thousands of dollars each.

“You don't sell wafers, you sell die,” Mack said. “The question is: how many die can I fit onto that wafer, and how many of those die yield, and therefore how many chips can I sell per wafer?”

The efficiency gap

There is some evidence of what that efficiency gap can look like in practice – albeit in memory rather than logic chips. In a June report, Morgan Stanley estimated that Chinese DRAM manufacturer CXMT was producing only around one-third as many bits per wafer as Western competitors. The analysts believed the older process node only accounted for around a third of that shortfall, but said access to lithography was a “hard ceiling” on Chinese memory development. “For advanced logic chips, in theory there could be other innovations to engineer around EUV, but they are not likely to be very efficient and effective,” said Douglas Fuller, a researcher at Copenhagen Business School, in comments to Tom’s Hardware Premium.

It is also why claims that China has reached a particular semiconductor process “node” need to be treated with caution. “If somebody says it's X node – the seven nanometer node, the five nanometer node, the three nanometer node – these words almost have no meaning,” Mack said.

That can be seen in SMIC’s latest chips. Reporting suggests its N+3 process represents meaningful progress towards 5nm-class manufacturing – but the actual measurements show it remains significantly less scaled than established 5nm processes from Samsung and TSMC. That doesn’t mean DUV has reached the end of its useful exploitation.

Stretching DUV's efficacy

Micron is an example of how far DUV can be stretched, producing competitive DRAM chips using DUV, multiple patterning and tight process control. Its 1-alpha generation of chips was developed without EUV. “They pushed 193 farther than any of the other memory makers did,” Mack said. “They were able to make very competitive chips with 100% 193 compared to Samsung and Hynix making them with many layers of EUV.”

Morgan Stanley believes CXMT’s planned move to 1-alpha DRAM – which it wants to use for HBM3e – is achievable without access to EUV, citing Micron as evidence. Indeed, “by the end of the decade, advanced packaging will allow firms to use DUV to produce the latest generations of DRAM,” reckons Fuller.

Micron also designed its products around the manufacturing technology available to it, rather than simply trying to recreate an EUV process on older equipment – something which could be a useful lesson for Chinese manufacturers. “If the entire ecosystem of 193 immersion were available to China,” Mack explained, “then they could probably push a long way with 193 multiple patterning, especially if they optimise designs for the fact that they're going to be using that.”

But Micron was making memory, whose highly repetitive structures make close co-ordination between chip design and manufacturing easier than it is for the much more complicated logic processors found in phones and computers.

“Memory is a lot easier than logic,” Mack said.

And even Micron eventually concluded that EUV was worth using. Its newer 1-gamma DRAM process uses EUV lithography, with Micron saying the technology helps it achieve more than 30% greater bit density per wafer than its preceding 1-beta generation.

EUV is hardly a magic wand, either. Mack points to stochastic effects – tiny random variations caused by the small number of photons involved in an exposure – which mean manufacturers can improve pattern control by increasing the EUV exposure dose. But it also pushes the cost back up quickly.

Because of that, Mack believes there is ultimately a limit to how far multiple patterning can economically substitute for EUV. “I would be hard pressed to really believe that a three nanometer or a two nanometer node is going to be economically viable without EUV,” he said.

That doesn’t mean Chinese chipmakers simply hit a technological wall and stop. They can keep pushing DUV while accepting larger dies, poorer yields, longer manufacturing times – or some combination of all three.

They can also throw capacity and money at part of the problem. Morgan Stanley assumes CXMT remains stuck on its 1-alpha process without EUV, yet still increases its share of global DRAM bit supply from 14% in 2026 to 16% in 2028 simply by building more greenfield capacity. The bank also expects China’s AI chip self-sufficiency to rise from 42% in 2025 to 70% by 2030 through new advanced-node capacity, improving yields and heavy state support – while EUV, HBM and advanced software leave a persistent gap. And so without EUV, the experts reckon China can only get partway to bridging the gap with the West. ““I would be hard pressed,” said Mack, “to really believe that a three nanometer or a two nanometer node is going to be economically viable without EUV.”

TSMC, the world's largest contract chip manufacturer, is seeking alternative machinery without rare-earth components to reduce its dependence on China-dominated materials and avoid disruptions to factory operations caused by the country's export controls. According to a Reuters report on October 22 citing people familiar with the matter, the Taiwanese company has begun approaching its equipment suppliers to explore whether they can provide factory automation equipment equipped with motors that don't require rare-earth materials.

TSMC supplies the extremely powerful Nvidia chips that are facilitating the AI boom. It also manufactures chips for Apple, Broadcom, Qualcomm, and numerous other tech and automotive companies. The company operates enormous, highly automated semiconductor fabrication plants. These factories use industrial machinery that relies on electric motors with powerful permanent magnets made from rare-earth elements such as neodymium, dysprosium, and terbium.

According to the U.S. Geological Survey (USGS), China accounts for roughly 70% of global rare earth mining. The International Energy Agency (IEA) says China also controls around 90% of refining and approximately 95% of the finished permanent magnets found in TSMC’s machines, giving Beijing a quasi-absolute monopoly over one of the most critical technology supply chains. In April 2025, the country placed seven medium and heavy rare earths and the magnets made from them under export controls, requiring exporters to seek case-by-case approval and export licenses, thereby choking shipments to manufacturers across the U.S., Europe, and Asia, including TSMC.

China expanded the controls on October 9, 2025, to include five additional rare earths, processing technology and equipment, and even products manufactured outside the country that contain more than 0.1% Chinese-origin rare earths, or are made using Chinese processing technology. It later suspended the October expansion for one year, until November 10, 2026. This has now been extended for an additional 90 days.

TSMC’s moves aim to reduce the risk that these controls will hinder production at its factories. Even with all other raw materials and machinery required to manufacture its chips, shortages of specialized motor components could complicate the maintenance, repair, or expansion of its production equipment. Several technological approaches allow motors to avoid rare earth magnets. Conventional induction motors, for example, generate torque using electromagnetic induction rather than permanent magnets. Switched-reluctance motors are another option, while some permanent-magnet motors can use ferrite magnets instead of rare-earth magnets. However, these technologies typically involve different trade-offs in efficiency, size, power density, precision, and control requirements.

Meanwhile, the rest of the world is undertaking the painstaking, drawn-out task of building a rare-earth supply chain outside China. Taiwan is reportedly pursuing domestic rare-earth production capabilities in collaboration with the United States, with both countries confirming their intent to reduce reliance on Chinese rare-earth and critical-mineral supply chains.

Taiwan's government is supporting the Industrial Technology Research Institute (ITRI) in establishing a pilot production line within three years that could supply about 50% of Taiwan's domestic rare-earth demand. Meanwhile, the U.S. is “working with Taiwan and other partners to develop alternative sources of supply, expand processing capacity and build more resilient supply chains,” according to the report. In February 2026, the Trump administration announced plans to create a $12 billion critical minerals stockpile to offset supply chain risks from China.

Intel on Wednesday announced that it had started installing production tools at its Fab 62 in Arizona, and the fab is on track for mass production by late 2028. The company also reported progress on its Ohio One manufacturing complex and confirmed that it has integrated High-NA EUV lithography into high-volume manufacturing (HVM). Meanwhile, Intel continues to invest in its leading-edge process technology R&D, advanced packaging, and photomask production capabilities in the U.S., which puts the company ahead of the competition.

"There is an important difference between technologies made in America and technologies that are truly American-made," wrote Naga Chandrasekaran, executive vice president and chief technology and operations officer, Intel Foundry. "The difference lies in the research and development process that transforms ideas into manufacturable technologies."

Fab 62 to begin operations in 2028

Intel completed construction of its Fab 62 shell some time ago; now it is time for the company to begin installing production tools, which is what it is doing now. Intel expects the new facility to become operational before the end of 2028, although it has not disclosed when it intends to begin high-volume production or which nodes it will produce.

Intel has not officially assigned Intel 14A to Fab 62, although the facility has been discussed as a potential manufacturing site for the node. Meanwhile, there is an important distinction between Intel's original plans for Fab 62 and its current commitments. When Intel announced Fab 52 and Fab 62 in Arizona, it said the two facilities would manufacture its most advanced process technologies, including Intel 20A (2nm-class) and 18A (1.8nm-class). Intel subsequently designated Fab 52 for Intel 18A manufacturing. Yet, Fab 62 remains unassigned.

Given Intel's manufacturing process roadmap disclosed earlier this year, Fab 62 will be able to make chips on 18A, 18A-P, and 14A nodes. Intel currently manufactures Intel 18A chips at the neighboring Fab 52, whereas Fab 62 could potentially accommodate either additional Intel 18A capacity or the company’s next-generation Intel 14A process technology. However, Intel has yet to confirm its plans for the facility.

The facility will become Intel's Fab 62, the sixth high-volume semiconductor manufacturing fab at its Ocotillo campus, which has served as one of the company’s primary production sites for decades.

Intel has also not revealed Fab 62's planned wafer processing capacity, or the amount of capital expenditures required to complete the facility. Nevertheless, the installation of production equipment indicates that the project has progressed beyond construction of the building itself. The new fab will expand Intel’s manufacturing footprint in Arizona, where the company already produces leading-edge processors and operates advanced packaging, assembly, and testing facilities.

Intel confirms High-NA EUV insertion into mass production

Another noteworthy disclosure concerns Intel's deployment of High-NA EUV lithography. Intel was the first chipmaker to install a commercial High-NA EUV scanner at its D1X fab near Hillsboro, Oregon, and subsequently integrated the tool into high-volume manufacturing to produce its Panther Lake and other chips.

The Gordon Moore Park at Ronler Acres in Oregon is where Intel develops its most advanced logic process technologies and initiates volume production of the latest processors. Usage of High-NA EUV to produce select tiles for Panther Lake CPUs at D1X is a natural fit for the development fab, as it helps Intel to better understand how these lithography systems work. Meanwhile, it seems (though Intel has not explicitly confirmed) that, for now, High-NA EUV scanners are used to produce the same circuits as Low-NA EUV machines, so the use of next-generation lithography systems does not necessarily provide significant advantages over existing litho scanners.

Ohio One reaches another construction milestone

Intel has also made progress with its 'Ohio One' manufacturing complex in New Albany, Ohio. Construction workers recently installed the first major structural truss at the site's first semiconductor fab, which represents a milestone in the development of the company's manufacturing operations in the state. The project is clearly an important part of Intel's long-term strategy to expand domestic production of chips using leading-edge process technologies for years to come.

Unfortunately, Intel did not provide an updated construction schedule for Ohio One or disclose when the first fab is expected to begin operations. Intel also did not reveal which process technology the facility will eventually use or the estimated manufacturing capacity it will provide. Therefore, while construction continues, which is good news, the announcement does not clarify exactly when Ohio One will contribute to Intel's output.

Other investments across the U.S.

In addition to leading-edge manufacturing capacity in the U.S., Intel continues to invest in advanced packaging technologies. Oregon serves as the company's main research and development center for advanced logic and 3D interconnect technologies, while Arizona hosts advanced packaging R&D, assembly, and testing operations. Intel uses its site in New Mexico to produce its complex multi-chiplet processors relying on advanced packaging methods — starting with modest EMIB and all the way to next-generation EMIB-T and Foveros technologies.

Also, Intel recently broke ground on a new photomask manufacturing facility in Santa Clara, California. The new facility will be an important part of Intel's supply chain in the U.S., as the company will be the only chipmaker in America to develop and produce chips using leading-edge nodes completely in the U.S. (both Samsung and TSMC currently lack leading-edge process R&D in America; they do not run their own photomask shops in the U.S., and Samsung has abandoned its plan to build an advanced packaging facility in Texas). Of course, Intel critically depends on tools from Europe and materials from Japan, but even as its major rivals invest hundreds of billions in their U.S. production capacity, Intel remains ahead.

To highlight its American supply chain, Intel disclosed that its U.S. operations involve more than 4,500 suppliers across 49 states, as its annual domestic expenditures exceed $29 billion. The company stressed that domestic semiconductor leadership requires not only wafer fabrication capacity but also research, process development, advanced packaging, and a comprehensive supply chain.

Elon Musk says ASML and other critical semiconductor equipment suppliers have expedited shipments for the ambitious Terafab semiconductor manufacturing facility, supporting his aggressive timeline for the joint megaproject between Tesla and SpaceX. He made the announcement during a live broadcast of SpaceX's Q3 2026 earnings call on X yesterday, October 20. Musk also said the company is targeting volume chip production at the project's primary facility in Gibbons Creek, Texas, by the third or fourth quarter of 2028, emphasizing that the timeline is highly aspirational and carries "big error bars."

"These are very aggressive dates, and we're very appreciative of ASML and all of our other suppliers in accelerating equipment deliveries in order to achieve this outcome," said Musk, CEO of both companies behind Terafab. SpaceX plans to manufacture its first experimental test chip at its research fabrication facility in Austin, Texas, around Q2 2027.

Aside from Terafab, Musk also outlined near-term ambitions for his AI companies during the broadcast, saying he expects them to have 2.5 to 3 gigawatts (GW) of computing capacity active by the end of 2026. He also stated he is highly confident about bringing an incremental 10 GW online in 2027, saying he "would be surprised" if they do not hit a total of 13 GW of AI compute by the end of 2027.

Meanwhile, the next-largest project by planned capacity, the now-restructured 10 GW Project Stargate, was expected to reach full capacity in the 2030s. Meta's 5 GW Hyperion also has a similar timeline. To achieve the 13 GW milestone, Musk revealed that SpaceX and xAI are aggressively procuring upcoming next-generation NVIDIA architecture. He announced plans to get a massive 440,000-GPU Nvidia "Vera Rubin" training cluster online by the end of Q2 2027.

Shifting back to Terafab, Musk also boasted that once fully scaled and operational, the sheer commercial value of Terafab's advanced chip output will place it within the top 20 global country GDPs from a single physical building. For context, the 20th country on the list is Switzerland, with a GDP of around $1.14 trillion. The facility is a planned multi-billion-dollar, vertically integrated chip factory in Texas, with an ambitious goal of manufacturing 1 terawatt (TW) of AI computing power per year. Terafab will fabricate logic, memory, and advanced packaging internal architectures in one place. The project's massive planned output has mandated various collaborations across the semiconductor supply chain. Terafab will utilize traditional extreme ultraviolet (EUV) lithography systems utilizing Intel's 14A manufacturing node technology.

Intel officially joined the Terafab venture in April 2026 to help co-develop and refactor silicon fabrication technology, providing access to its state-of-the-art 14A manufacturing process. ASML, the world's sole commercial supplier of the $400 million EUV lithography systems required for high-volume, leading-edge chip production, is perhaps the project's most critical partner. Terafab's first EUV tool was reportedly slated for delivery in mid-2027, according to unofficial sources. It remains unclear if this is the expedited timeline Musk referred to in the broadcast.

Other major suppliers include American equipment manufacturers Applied Materials, Lam Research, and KLA Corporation, as well as Japan's Tokyo Electron. These companies will provide front-end processing, metrology, and process control machinery. Tesla and SpaceX are also in talks with about 10 South Korean equipment makers, including Hanmi Semiconductor, known for advanced packaging equipment, and HPSP, a high-pressure hydrogen annealing equipment manufacturer, as well as firms providing specialized piping components and process valves.

Musk's announcement says that several of these suppliers are expediting supply to Terafab, even as capacity remains tight across the semiconductor supply chain. The facility, which aims to mitigate future shortfalls of cutting-edge AI processors from external foundries like TSMC, will supply the chips for Musk's xAI clusters, self-driving vehicles, Optimus humanoid robots, and SpaceX's orbital AI data center, as well as the broader AI industry.

However, many experts have questioned the validity of Musk's 1 TW Terafab ambition. For context, research firm Gartner estimates the total global AI-optimized data center capacity is roughly 44 GW as of late 2026, 4.4% of Terafab's planned output. Although global AI computing capacity has grown by roughly 3.3x to 3.4x per year since 2022, according to EpochAI.

Three contract workers died, and one more is in intensive care after an accident at the construction site for TSMC’s 2nm Fab 22 in Kaohsiung, Taiwan, reports Taiwan’s Central News Agency. The Southern Taiwan Science Park (STSP) Bureau suspects the cause was a broken bolt on a steel connection plate that sent the workers and steel components tumbling. Steel hoisting on the project has been halted, and the STSP has sent labor inspectors to investigate. The accident is not the first of its kind but rather follows at least a half dozen others since September 2024 at TSMC construction sites in Taiwan, according to local reports. Each of those earlier accidents killed one worker.

Local police said that the men were welding a steel beam on an upper floor and fell with it, while the STSP said the workers were performing steel-structure hoisting and installation when a third-floor connection-plate bolt apparently broke.

10 emergency vehicles were sent to the site with 22 personnel, and all four men involved in the incident were taken to the hospital. On-site medical staff gave first aid, but three of the workers died despite resuscitation efforts, and the fourth was moved to intensive care. The workers were employed by a contractor working on the fourth phase of the complex’s construction, and TSMC said the area was within that contractor’s scope of work.

According to the report, TSMC stopped the related construction work on its own and is working with authorities and supervising the subcontractor’s follow-up.

The Fab 22 complex, located in Kaohsiung’s Nanzi District, is part of the science park and is being built to accelerate 2nm manufacturing. TSMC entered high-volume 2nm, or N2, manufacturing in the fourth quarter of 2025, including at Fab 22. The complex has five phases planned, with a total investment TSMC puts at more than NT$1.5 trillion, or about $46 billion. The accident happened on the construction side, not in a producing fab. Kaohsiung’s deputy mayor said construction on Phase 4 began in August 2025, with operations expected in the fourth quarter of 2027.

Business Today reports that TSMC fab construction has increased, from four fabs a year in 2017–2024 to nine a year in 2025 and 2026. The deaths come as the company plans for 13 new leading-edge and advanced-packaging fabs in Taiwan, with company-wide capex of $60 billion to $64 billion this year.

The faster pace has encouraged the addition of a contractor’s safety record as a weight in selection and a plan for a Taiwan Semiconductor Construction Engineering Safety Association with construction partners. TSMC Chairman C.C. Wei said at last year’s shareholders meeting that safety cannot be compromised, and the company’s 2025 annual report said it will keep investing in fabs across several locations in Taiwan “with a strong emphasis on construction site safety.”

Cliff Hou, TSMC senior vice president and deputy co-COO, told Business Today that increased worker count and overlapping construction have raised the risk, requiring careful supervision, and that TSMC’s contractor lost-time injury rate had fallen about 42% from last year’s high as of late May, when the publication toured the Nanzi site to see the overhaul. It’s too early to call the program a failure, with the cause as yet unknown.

The accident comes less than a week after an explosion killed two people at Intel’s chip plant in Israel, though that was an operating fab rather than a construction site. Both accidents come as chipmakers race to meet demand, with global chip sales passing $1 trillion through August, according to the Semiconductor Industry Association.

The STSP’s findings will determine what penalties, if any, will fall under Taiwan’s Occupational Safety and Health Act, while it assists the victims’ families. No date has been given at this time for that or for the Phase 4 steel hoisting restart. Nor has TSMC commented on any schedule impact.

Intel has asked the Federal Communications Commission (FCC) to make an exception for the automated guided vehicles (AGVs) that the company uses to transport the sensitive silicon wafers and other materials, containers, and supplies needed to make the most advanced chips in its fabs. According to Bloomberg, the American chipmaker fears that its AGVs would fall under the blanket prohibition against foreign-made robots after they were added to the FCC’s Covered List.

AGVs are niche machines that chip fabs use to transport materials and supplies between tools and sections of the fab, helping ensure that the cleanroom conditions required for each manufacturing process are maintained. This makes them critical equipment for U.S. semiconductor manufacturing, but, apparently, there are no suitable domestic alternatives for these devices at the moment. Intel’s current fleet of AGVs requires continuous maintenance, including software and firmware updates, and if it’s forced to find a local supplier for its AGVs, the company says that it would take years, crippling the United States’ chipmaking efforts.

The biggest AGV suppliers are Japanese companies like Murata Machinery and Daifuku Co., while a few smaller businesses from South Korea and Taiwan are also trying to break into the market. It’s unclear why these companies haven’t applied for a conditional approval yet, which would allow them to continue selling these products in the U.S. while also promising Washington that they’ll set up a manufacturing base in the country. This is something that Netgear has already done, allowing it to continue selling its foreign-made routers despite being an American company.

Intel says that it remains unclear if updates to its AGVs would break compliance with the FCC, and that it’s asking the agency to issue a conditional waiver “out of an abundance of caution to ensure the ongoing operation of these specific AGV units.” While Team Blue is the only company concerned about AGVs at the moment, other chip manufacturers would likely need a similar waiver in the near future, especially as they build more fabs in the U.S. This includes TSMC, which is planning to build 12 more fabs and four packaging facilities in Arizona, Samsung, with its new Taylor, Texas, fab, and even Elon Musk’s Terafab, which has already begun construction.

Washington has been using the FCC to force companies to invest in American manufacturing. Its blanket bans on foreign-made products like drones and routers have affected some of the biggest brands in the U.S., including DJI and TP-Link. While these bans do not outright ban the sale of all products made by these companies, especially those that have already been approved before, they make it impossible for them to introduce new products and even release software updates to their existing product line. The FCC eventually walked back on the software update ban, but they still would not be able to register new products unless they build them in the U.S.