A new semiconductor firm, TYLsemi (pronounced Tile Semi), publicly revealed itself this month, alongside $43 million in early-stage funding and an ambitious plan to simplify the development of custom processors for AI infrastructure.

Dozens of contract chip designers can develop custom processors of different complexity. However, only a few companies can offer custom silicon design services using standard chiplets to speed up and derisk the development cycle. TYLsemi is aiming to join their ranks. We spoke to their founders to find out how the nascent business might pull it off.

Emerging from stealth

Rather than compete solely as another custom ASIC design house, TYLsemi intends to offer reusable, standards-based connectivity, power delivery, and eventually memory chiplets that customers can combine with their own differentiating compute silicon to build a unique system-in-package. For companies that do not intend to conduct semiconductor development themselves, TYLsemi will also provide an end-to-end service that includes design and implementation of a differentiating chiplet, packaging, qualification, and high-volume production, essentially enabling companies without any silicon development skills to offer their own multi-chiplet processors.

TYLsemi was co-founded by Mohit Gupta and Sunil Bhardwaj, semiconductor veterans who have led global engineering, operations, and business teams at Alphawave, SiFive, Cadence, Rambus, and other chip companies, and who collectively have plenty of experience with both standard and custom silicon. Mohit Gupta, a co-founder and chief executive of TYLsemi, believes that the time to establish a company that specializes in pre-approved chiplets and custom ASIC design is right now.

"Chiplets have been discussed for seven or eight years, but several things have changed in the last three or four years," Gupta told Tom's Hardware Premium. "First, advanced packaging has matured significantly. There are now multiple 2.5D and 3D integration options in volume production. Customers are not limited to one packaging technology or supplier; there are options from foundries and OSATs, including TSMC, Intel, ASE, and Amkor. Second, die-to-die standards have arrived. In the past, most chiplet implementations relied on proprietary interfaces. UCIe is now moving into production deployments, including at hyperscalers, which makes heterogeneous integration much more practical. Third, supply-chain resilience has become critical. Customers increasingly want modular and potentially multi-source strategies rather than a single point of failure. Those factors have created an environment that did not exist four or five years ago."

AI accelerators will be among the primary applications to benefit from multi-chiplet design, as we have already learned from AMD and Nvidia.

"The AI accelerator market is on track to reach $604 billion by 2033, and custom silicon XPUs built for specific hyperscaler workloads are the fastest-growing segment," Gupta said. "At that scale, chiplet-based design is no longer optional, yet there is no pure-play chiplet company serving this market with a full portfolio. TYLsemi closes that gap with standards-based chiplets combined with UCIe-based die-to-die connectivity, XPU-aware design, packaging, and integration — giving customers a fast, proven path to AI-era silicon."

Chiplet economics

The vast majority of AI and HPC accelerators today feature large die sizes, in many cases approaching the size of a reticle. However, as modern process technologies are becoming more complex, foundries tend to increase their quotes for new nodes. A leading-edge wafer used to cost around $15,000 to process around five years ago, but today that price is around $30,000. As a result, large chips at a size close to the reticle limit implemented on a leading-edge node become an option for a select few chip designers who can afford it. For newcomers, multi-chiplet designs enabled by advanced packaging and standardized interconnects such as UCIe start to make a lot more sense.

"Once dies get into the 500 – 600 mm² range, the yield curve becomes increasingly difficult. Timing closure on a reticle-sized die is also challenging," Gupta explained. "I have worked on a reticle-sized accelerator, and getting from 99% to the final 1% can require disproportionately more engineering effort."

TYLsemi estimates that its chiplet approach could reduce total cost of ownership by 57% at a volume of 100,000 devices, from $350 million for a monolithic 700 mm² 3nm-class chip to $150 million for a design combining a 500 mm² 3nm-class compute die with four 100 mm² I/O chiplets built on an N-1 process. TYLsemi believes that the unit price of a monolithic chip would be $3,000, whereas the cost of an SiP would be around $600. The company attributes the saving to higher yields, reusable I/O silicon, lower IP licensing and engineering costs, and substantially lower per-unit silicon costs. However, the company stresses that the figures are illustrative estimates rather than actual manufacturing costs. Additionally, multi-chiplet designs can enable faster product refreshes compared to large monolithic dies as they are faster to develop and yield.

"Compute may move to 2nm or A14, while high-speed I/O can remain on 3nm, since I/O does not scale in the same way as logic," Gupta said. "Our power-delivery chiplets can use an even less advanced process. Customers therefore do not have to use the most expensive silicon real estate for every function. […] There is no single answer for every design. You have to determine the right disaggregation points based on the architecture, thermal requirements, package, and how multiple accelerators communicate. […] The exact partitioning will vary by application, but you still get a better total cost of ownership."

TYLsemi primarily targets AI infrastructure, so it generally envisions multi-chiplet designs to be used for AI accelerators, data-center CPUs, high-performance computing, networking and telecom silicon, and heterogeneous SoCs. However, TYLsemi has also ignored the fact that multi-chiplet designs are already widely used for consumer CPUs and GPUs.

Foundation chiplets

At the core of TYLsemi's proposition are its foundation chiplets, which are reusable building blocks intended to handle common non-compute functions in custom AI and infrastructure processors and are implemented using various process technologies from TSMC. The foundation chiplets include the following:

• TYL.IO — a family of connectivity chiplets that includes TYL. IO PCIe, a 32-lane PCIe 7.0/CXL chiplet connected to the compute die via UCIe; TYL.IO Scale, a 224G+ SerDes for ESUN/UALink scale-up connectivity; and TYL.IO EIC for co-packaged optics.
• TYL.Power — a 16nm in-package IVR chiplet with embedded passives, designed to provide power closer to compute dies and use closed-loop control and die telemetry to improve power delivery.
• TYL.Mem — a planned family of memory-connectivity chiplets. TYLsemi has not yet disclosed the architecture or specifications, though it is safe to assume they are talking about memory controllers and PHYs.

Not all of these chiplets will be available immediately, as the company has certain priorities amid limited resources.

"The first TYL.IO product disaggregates the PCIe functionality that would normally sit on a large server processor, it is a 32-lane PCIe Gen7/CXL chiplet connected to the host compute die using UCIe," Gupta explained. "The idea is that the CPU cores can move to 2nm, A14, or another leading-edge process, while the I/O chiplet remains on 3nm. The next product in the family will address scale-up connectivity between XPUs within a rack using high-speed SerDes. That device will be considerably larger, with around 72 lanes and approximately 14 TB/s of bandwidth. We also have an EIC roadmap for co-packaged optical connectivity. We expect samples of our first I/O product in the second half of 2027."

These chiplets can be used as standalone components or integrated with a customer's compute dies designed by the customer to TYLsemi through TYL.Forge, TYLsemi's end-to-end custom silicon platform.

TYL.Forge

TYL.Forge is arguably one of the key enablers of TYLsemi's business, as the program is aimed at companies that have their own compute architecture or even a compute die, but cannot build their own SiP or manage the entire semiconductor supply chain.

"There are larger custom silicon companies in the market, but many of them focus on a relatively small number of customers that can generate billions of dollars in annual business," Gupta explained. "We see an opportunity among emerging AI companies and system companies that need advanced custom silicon but also need a partner capable of taking responsibility for the entire implementation and supply chain."

Such clients can provide their proprietary compute RTL, while TYLsemi handles physical implementation and integrates the resulting compute die with its pre-validated connectivity, power, and eventually memory chiplets. The company then manages tape-out, packaging, assembly, testing, qualification, and high-volume production.

"For example, a customer building a large accelerator can bring us its matrix-multiplication engine," Gupta said. "We can implement the custom compute die and integrate it with our chiplets, so the customer does not have to reinvent the I/O and other common functions. This reduces risk and time to market."

In fact, TYL.Forge appears flexible about where the customer enters the development process. TYLsemi describes the platform as covering everything from architecture and front-end design through implementation, tape-out, assembly, qualification, and production. So instead of RTL, customers can come to TYLsemi with an architecture/concept, and then the company will help develop and implement the silicon. Nonetheless, TYLsemi does not intend to invent the customer's core compute architecture itself. In addition, customers can bring in an existing compute die, which TYLsemi can combine with its chiplets, package, test, and bring to production.

"We are also talking with companies developing Arm- and RISC-V-based server processors," Gupta said. "They can develop the architecture, while we implement the rest of the silicon and bring the product to production. That gives customers an economic and engineering advantage because they do not need to build teams for every part of the chip."

The key advantage of TYL.Forge is the reuse of pre-validated components. Instead of developing common functions such as PCIe connectivity and power delivery for every new processor, customers can use TYLsemi's pre-validated foundation chiplets and focus engineering resources on differentiated compute architectures, software, and system design. In theory, TYLsemi could integrate third-party chiplets (not from a customer, but from a third-party chiplet provider). Still, the company's focus remains on offering its own pre-validated chiplets and custom silicon with SiPs it builds.

"Potentially, [we could integrate third-party UCIe chiplets into a TYLsemi-based system], UCIe has done a very good job defining the electrical interface, but the ecosystem is still maturing at the protocol level," Gupta explained. "In some cases, if we provide a chiplet to a customer, we may also need to provide or enable the UCIe IP on the other side of the connection. We are committed to UCIe and industry standards because standardization ultimately wins. […] We can consider customization for a large strategic customer or hyperscaler, but we do not want those projects to derail our standard product roadmap. […] Even when customers buy our standalone chiplets, I expect many of them will ask us to handle packaging and testing because heterogeneous integration and supply-chain management are difficult "

TYLsemi estimates that its approach can cut development time and cost by up to 50% compared with traditional custom silicon programs. In the best-case scenario, TYLsemi envisions that the development cycle can shrink considerably compared to today's cycles that can be two, three, or more years long. According to TYLsemi, once a customer provides sufficiently mature RTL or a netlist, the company can take a custom compute die to tape-out in around six to nine months or so, which includes fabrication, assembly, testing, and qualification.

"If a customer provides mature final RTL or a netlist and uses our standardized I/O chiplet, we believe we can take the custom compute die to tape-out in approximately six months in some cases," Gupta explained. "More generally, our target is six to nine months from a mature design to tape-out. The architecture and front-end phase is more customer-dependent. For a first-generation product, that can take around six months; for a more mature second- or third-generation design, it could be closer to three months, and some of that work can overlap with implementation. After tape-out, fabrication can take roughly four to five months depending on the process, followed by perhaps another two months for assembly, testing, and qualification. If the architecture is already mature, it may therefore be possible to reach production samples in about a year."

Still, the company stresses that architecture development and implementation typically include feedback loops, which greatly slow the development process. This is why the company provides the relatively conservative '50%' figure.

TYL.IO and TYL.Power samples will be available to qualified customers in 2027, in partnership with TSMC, and the company is looking forward to designing processors for its clients in time for them to reach the market in 2029 – 2030.

Speaking of TSMC, TYLsemi will initially only offer designs and services adhered to the TSMC ecosystem, though eventually it may offer other options for packaging technologies, such as Intel's EMIB and Foveros, or Amkor's packaging methods.

"We are initially focused on the TSMC ecosystem, but we also intend to explore other advanced-packaging supply chains," Gupta said. "We do not want to limit ourselves to one packaging option. Over time, that could include other OSATs and packaging technologies. […] That could include Intel, ASE, Amkor, or others. Amkor, for example, is building significant packaging capacity in Arizona."

Intel will design, package, and fabricate Fortinet's sixth-generation Security Processor (SP6) on its Intel 4 node, the companies announced on July 21, giving the process its first named external foundry customer, roughly three years after it entered production. Intel told Tom's Hardware the agreement reflects "the strategy Intel outlined for Intel 4 several years ago," including support for custom networking ASIC workloads. Intel's own record from those years reads differently, however, with the company's 2021 roadmap having scoped Intel 4 to two internal products. And through 2022, it told engineers and investors that Intel 3, not Intel 4, would be its first process offered to foundry customers.

Intel 4's record

Intel's Accelerated announcement back in July 2021 said that Intel 4 would reach production readiness in the second half of 2022 for products shipping in 2023, naming "Meteor Lake for client and Granite Rapids for the data center." The release and its accompanying fact sheet, however, contained no reference to foundry customers, networking, or custom ASICs on the node.

At VLSI 2022, Intel disclosed that it wasn't building a high-density library for Intel 4 and that Intel 3 would be the first new node offered through what was then Intel Foundry Services. A 2024 post on Intel's own foundry blog describes Intel 3 as "Intel Foundry's first leading-edge process node," and Intel's fiscal year 2024 annual report listed the processes available to external customers as 18A, Intel 3, Intel 7, Intel 16, and a 12nm node co-developed with UMC. Intel 4 appears nowhere on that list.

Ericsson's RAN Compute processors, announced in November 2023, were built on Intel 4, so Fortinet's part won't be the first third-party silicon to come off the node. That work grew out of a bespoke Intel-Ericsson collaboration, though, and Ericsson's formal foundry agreement with Intel, announced in July 2023, covered 18A. Fortinet is the first named customer buying Intel 4 as a foundry service, and the first cybersecurity vendor on any Intel node. The Ericsson engagement is also the closest thing in the public record to networking silicon on Intel 4, two years after the strategy Intel now says it outlined for the node.

Fab 34 economics

Intel 4 entered high-volume manufacturing at Fab 34 in Leixlip, Ireland, in September 2023, producing the compute tile for Meteor Lake-based Core Ultra chips, and shares the fab with Intel 3. Intel sold a 49% stake in the facility to Apollo-managed funds for $11.2 billion in June 2024, then bought it back in April 2026 for $14.2 billion, funded with $7.7 billion in cash and $6.5 billion in new debt. That buyback returned 100% of Fab 34's wafer economics to Intel at a premium of roughly 27%, and it only pays off if the fab's EUV capacity stays loaded.

Meteor Lake is aging out of Intel's lineup as 18A-based Panther Lake ramps through 2026, which leaves open the question of what fills Intel 4 capacity next. A multi-generation firewall ASIC program is a reasonable answer with mature yields, a customer that values supply stability over bleeding-edge density, and a part Intel described as tailored for cost-sensitive applications. Intel said in April that yields were improving across Intel 4, Intel 3, and 18A.

Fortinet's supply chain

Fortinet's 2025 annual report names Renesas and Toshiba America as the contract manufacturers for its ASICs, utilizing foundries in Taiwan and Japan operated either by TSMC or by the contract manufacturers themselves. The current SP5, a monolithic 7nm Arm-based SoC announced in February 2023, sits in that supply chain, so SP6 on Intel 4 moves Fortinet's next flagship security processor out of a TSMC-linked flow and into Intel's. The disaggregated design language in the announcement points to a chiplet-based part, a first for Fortinet's SP line.

Fortinet re-engineered three FortiGate models in 2022, the 70F, 600F, and 3700F, to accept alternative components during the chip shortage, and CMO John Maddison told SDxCentral at the time that the company wouldn't wait for parts to arrive in 2023. The "resilient and diversified" supply chain used in the SP6 press tracks back to that experience. Ken Xie called Fortinet "the #1 firewall leader with a 55% unit market share" in the company's 2025 results in February, with approximately six million FortiGates deployed, so there’s real, substantial volume here even if the parts are relatively inexpensive.

Intel Foundry reported $307 million in external revenue for 2025, up from $159 million the year before, against total foundry revenue of $17.8 billion and an operating loss of $10.3 billion. External revenue in Q1 2026 was $174 million. Fortinet's hardware business runs at roughly 30% of its revenue, and, per analysis from ServeTheHome, SP6 is ultimately a component of a portion of an annual hardware stream around $2 billion, so the deal won't move Intel's foundry line materially, even at full production.

CEO Lip-Bu Tan told CNBC in May that he expected commitments from multiple foundry customers in the second half of 2026, and Intel told investors in January that two prospective customers were evaluating 14A test chips. The SP6 announcement comes inside Tan's stated window, and it finally gives Intel something its foundry marketing has lacked in a named customer with shipping volume on a node with mature yields. Meanwhile, an 18A or 14A commitment from a major external customer is still missing, and Fortinet's cost-sensitive parts on a 2023 node don't substitute for one.

Intel and Fortinet have announced a strategic collaboration to develop the Fortinet Security Processor 6 (SP6), the next generation of the custom silicon behind Fortinet's FortiGate firewalls. Intel will contribute chip design, advanced packaging, and manufacturing to the SP6 program, making Fortinet the first cybersecurity vendor named as an Intel silicon customer.

Intel told Tom's Hardware that SP6 will be built on Intel 4, the EUV process the company has so far used only for its own products, making Fortinet both the first cybersecurity vendor named as an Intel silicon customer and the first named external customer for the node. However, the announcement specifies no production timeline, and it comes in the same Q3-Q4 2026 window in which CEO Lip-Bu Tan said the company expects commitments from multiple foundry customers.

SP6 will draw on what the companies described as Intel's expertise in disaggregated semiconductor design and advanced packaging tailored for both AI-enabled and cost-sensitive applications.

That points to a chiplet-based part, which would be a departure from the current SP5, a monolithic 7nm Arm-based SoC that Fortinet launched in 2023 for its entry-level and mid-range FortiGate appliances. The deal will help Fortinet "accelerate and strengthen our ASIC strategy," said Ken Xie, founder, chairman, and CEO of Fortinet, in the announcement.

Intel 4 was the company's first process node to use EUV lithography and entered high-volume manufacturing at Fab 34 in Ireland in September 2023, where it produces the compute tile for Meteor Lake-based Core Ultra chips. The node didn't appear among the processes Intel listed for external foundry customers in its fiscal year 2024 annual report, which named 18A, Intel 3, Intel 7, Intel 16, and a 12nm process co-developed with UMC. Intel said the SP6 work reflects plans it laid out for Intel 4 several years ago, including support for custom networking ASIC workloads.

Microsoft agreed in early 2024 to build an unnamed custom chip on Intel's 1.8nm-class 18A node, a deal that reportedly covers a next-generation Maia AI processor. That announcement followed a similar pattern, with no product details, node variant, or timeline at signing and specifics emerging over the following 18 months.

Intel CFO David Zinsner said in March that the company was fielding inbound interest in 18A-P from prospective foundry customers as yields improved, and Tan told CNBC in May that foundry commitments were expected in the second half of 2026.

Fortinet does bring real volume, though, if not marquee volume. IDC ranked Fortinet first in firewall appliances shipped as of early 2023, with a 48% unit share. The company ships its own ASICs across its entry-level and high-end FortiGate ranges, and SP6 extends a silicon program now in its sixth generation.

Neither company committed to work beyond SP6, though the release described the agreement as a starting point, with further collaboration on chip technology and manufacturing under discussion.

TSMC intends to raise base quotes on advanced chip production services by up to 10%, according to Nikkei, which cites people with knowledge of the matter. The price hike reflects increased demand for sophisticated processors by the AI sector, raising costs of tools and materials, as well as amplified investments in new production capacities.

For advanced process technologies — which TSMC considers 7nm-class and below — TSMC plans to raise baseline prices by 5% to 10%, depending on the particular production node and customer, the report claims. Furthermore, customers that need additional HPC chip capacity beyond their original volume requirements will reportedly have to pay another 10% to 15% premium on top of the standard increase, which means that some services will get a price hike of around 25%, if the report is accurate.

TSMC also intends to increase prices for mature manufacturing technologies, including its 12nm, 16nm, and 28nm-class nodes as well as other legacy fabrication technologies, the report claims. Increases could reach 10%, although certain nodes will reportedly see smaller adjustments, according to Nikkei.

Advanced technologies generated around 77% of the foundry's revenue in Q2 2026, whereas mature nodes accounted for 23%, which essentially means that TSMC is hiking prices on all of its services.

The company reportedly began discussing the new pricing with customers around June and completed negotiations in July. Rather than introducing higher rates immediately, TSMC opted to implement them from the beginning of 2027 to give clients like Apple, AMD, Nvidia, and MediaTek additional time to accommodate the changes and adjust their prices accordingly.

Since TSMC produces the lion's share of advanced processors for AI, HPC, networking, and smartphone applications, its price hikes will inevitably create a ripple effect in the industry and will make almost all electronics more expensive.

TSMC is not alone in raising prices these days. Vanguard International Semiconductor has also raised prices, while UMC began implementing increases in July. Also, memory makers have increased prices significantly, making TSMC management jealous. Intel also recently increased prices of its client and data center CPUs, citing market demand.

"I am really jealous about memory companies' 86% gross margin," said C.C. Wei, chief executive of TSMC, during the company's earnings call with financial analysts and investors. "86% [margin at memory makers] – 68% [margin at TSMC], I will be happy about that."

TSMC rarely comments on its prices to a large degree because they vary based on volumes and relationship with a particular client. Nonetheless, the head of the company stressed that the company has no intentions to increase prices suddenly or dramatically.

"So we do not suddenly increase our price by which I like to have 4x or 5x," Wei said. "You cannot survive for that kind of... for your customer to survive for that kind of price increase. So we earn our value, and we make sure that our profit, our gross margin, is enough for our long-term sustaining expansion, that is to the benefit of my customers and TSMC also, that is our philosophy."

An analysis of Huawei's Kirin 9030 system-on-chip (SoC) for smartphones conducted by SemiAnalysis revealed that SMIC's third-generation 7nm-class fabrication technology (N+3) has smaller metal pitch than Intel's 18A fabrication technology and that China's leading foundry has managed to achieve transistor density on par with manufacturing process that rely on EUV lithography. But does this make SMIC's N+3 node as competitive as Intel's 18A or TSMC's N2 and N3? Not really.

SemiAnalysis' teardown indicates that SMIC's N+3 fabrication process supports a minimum metal pitch of 32.5nm, which is nominally tighter than the approximately 36nm pitch used for many high-performance cells in Intel's Panther Lake CPU, even though 18A can support approximately 32nm metal pitches. The video from SemiAnalysis and High Yield does not reveal other important characteristics of SMIC's N+3, such as contacted gate pitch (CGP), standard cell height (tracks or nm), or fin pitch, so we cannot make direct comparison of this node to Intel's or TSMC's technologies. What it does reveal is estimated transistor density of around 113.4 million transistors per square millimeter (Mtr/mm²), which is even higher than transistor density of TSMC's N6, 107.7 Mtr/mm².

TSMC's N6 uses multiple EUV layers, so achieving higher transistor density without using EUV lithography is an indisputable technological achievement of SMIC. The foundry achieves this density by using DUV multi-patterning, including self-aligned quadruple patterning on the tightest layers, and extensive design-technology co-optimization (DTCO). In addition, SemiAnalysis believes that SMIC used techniques like reduced fin counts, placing contacts directly over active gates, and tightening cell isolation. Such methods allow for increased transistor density, but at the cost of increased process complexity, cost, yield risks, and design constraints.

Meanwhile, transistor density does not equal overall process competitiveness. Despite its compact layout, the Kirin 9030 reportedly delivers performance comparable to flagship application processors from roughly three years ago and has a substantial energy-efficiency disadvantage compared with modern Apple, Qualcomm, MediaTek, and Samsung designs. Huawei's highest performing CPU core is characterized as roughly Cortex-X2-class in IPC, while Apple's much smaller efficiency cores reportedly outperform it in integer workloads and consume considerably less power.

Given the fact that Kirin 9030 is neither a performance nor efficiency champion, the provocative comparison with Intel 18A is not exactly justified. Although SMIC N+3 has 32.5nm minimum metal pitch that is nominally tighter than the approximately 36nm pitch used in Panther Lake, 18A offers both higher transistor density and considerably higher performance efficiency. In addition, 18A uses gate-all-around transistors and backside power delivery, which make it particularly suitable both for mobile SoCs and for data center applications.

SemiAnalysis concluded that while export restrictions have slowed China's technological progress, progress is still being made. SMIC could potentially continue increasing density by tightening upper and lower metal layers, shorter standard cells, smaller gate pitches, and eventually backside power delivery. If the company continues scaling, N+4 could approach TSMC N5-class density, while N+5 with backside power might reach Intel 18A-class density, according to SemiAnalysis. Still, transistor density alone does not necessarily bring substantial improvements of performance or power efficiency.

ASML is reportedly considering increasing prices of its existing Low-NA EUV lithography tools. The potential price hikes have already upset TSMC, ASML's largest client, reports The Information. But can ASML rapidly raise the prices of the tools it sells to chipmakers? Price adjustments are not going to happen overnight, said Roger Dassen, CFO of ASML, said during the company's quarterly earnings call. But there is one thing to remember about ASML's price hikes: They are going to affect the entire semiconductor industry.

"When it comes to Low-NA [EUV tools] pricing, of course, you know that we keep on increasing the productivity of the Low-NA tool, [which] gives us a pretty strong runway for potential price improvements going forward," said Roger Dassen, chief financial officer of ASML, during the company's quarterly earnings call. […] Given the long order lead times that we have, that does not translate into pricing effects tomorrow."

ASML just reported record results for its second quarter of 2026, with total net sales of €9.326 billion ($10.67 billion) and net income of €2.918 billion ($3.338 billion). The company now expects net sales between €43 billion ($49.2 billion) and €45 billion ($51.5 billion) in 2026, a range that comfortably exceeds its own guidance and the expectations of industry analysts.

More complex, more expensive

ASML has generally increased the average selling price of EUV scanners over successive generations as they increase in complexity and productivity, so the idea of higher pricing of EUV tools is not particularly new. The company calls the concept of 'value-based pricing' and gradually increases its average selling price (ASP) based on the value that its tools provide to its operators.

Early ASML Twinscan NXE systems were commonly discussed in the roughly €100 million–€120 million ($115 million-$137 million) range, while later production models such as the NXE:3400C and NXE:3600D moved toward roughly €140 million–€170 million ($160 million-$195 million). The latest NXE:3800E is climbing even further. High-NA EXE systems represent another major step up, at more than €350 million ($400 million) per machine according to industry reports.

Meanwhile, both productivity and performance of ASML's Twinscan NXE systems have been steadily increasing: While the NXE:3400C and NXE:3600D can process 160 – 170 wafers per hour (WPH) and feature a matched machine overlay (MMO) of ≤ 1.1nm, the NXE:3800E and NXE:3800F increase productivity to 220 WPH and 260 WPH, respectively, while increasing MMO to 0.9nm. With the NXE:4200G and NXE:4200H (which will likely feature an all-new light source), we are looking at productivity beyond 300 WPH and MMO of ≤0.8nm - ≤0.7nm.

ASML makes no secret that more advanced EUV lithography tools carry a higher average selling price than their predecessors.

"You should also recognize that the tool mix that we are going to ship next year is a different tool mix from the tool mix that we shipped this year," Dassen said. "When it comes to EUV in particular, the tool mix that we are going to ship next year will be EXE: 3800E and EXE:3800F [tools], while this year it is a combination of EXE:3600D and EXE:3800E [systems]."

ASML's value-based pricing logic is essentially: if an upgraded Low-NA machine processes more wafers and therefore generates more economic value for a fab, ASML can capture part of that additional value through a higher system price. This is what ASML has been doing for some time. That said, the important nuance in Dassen's statement is that he appears to be discussing further price increases for Low-NA EUV tools.

ASML's EUV dominance

ASML is the only supplier of EUV lithography systems on the planet; every single chipmaker must comeq to the company to get one of these scanners, so the company sells these machines years in advance. This year, the company expects to have the capacity to build 65 EUV tools and intends to increase capacity by 30% next year to around 84 – 85 EUV systems. In 2028, ASML plans to produce 110 EUV scanners.

"For 2027, we are now close to being fully covered with orders for Low-NA EUV, and we are planning to increase our Low-NA EUV capacity by around 30%," Dassen said. "Looking ahead to 2028, we have already received a significant number of Low-NA EUV orders. Strong demand forecasts from our customers have led us to investigate a further 30% capacity increase for that year."

Given the strong demand for ASML's tools, the company is in a position to increase prices, at least according to the rules of the free market. As always, comments on pricing are made in opaque corporate language, so one can make a lot out of it, or nothing at all.

"Clearly, the environment that we live in today, with the [substantial] value that our products bring to customer, of course, gives us flexibility on pricing, more so than what you would have seen in the past," Dassen said. "Of course, we are executing on that as well."

However, it is not that easy for ASML to just hike prices overnight, and there are important things to note. When ASML gets an order, and that order enters the reported backlog (which totaled €38.8 billion as of late Q4 2025), it already carries a sales value (with a possibility of inflation adjustments), so there is necessarily an agreed or otherwise contractually determined price basis attached to it.

This makes Dassen's comments particularly interesting. If ASML is already close to fully booked for 2027 Low-NA EUV capacity and has received a significant number of Low-NA orders for 2028, then much of that capacity is already represented by customer orders with associated sales values. As a result, unless ASML can subsequently renegotiate the fixed price before delivery, it cannot hike prices on tools that it intends to ship in 2027 and part of 2028. This essentially means that ASML could only book new orders that it intends to ship in 2028 (presumably for the second half of the year) and onwards at higher prices. However, ASML has not confirmed this directly.

ASML's next-generation NXE:4200G is on track to arrive in 2029. That scanner is poised to be more expensive than the NXE:3800E/NXE:3800F anyway, so the company's Low-NA EUV ASPs will inevitably get a bump that year. Of course, ASML is set to continue shipping its EXE:3800-series after 2029. The big question is whether the company will adjust the prices of these units that will ship starting in 2028 or not.

We do not know the answer to this question, unfortunately. But during the conference call, ASML's financial chief implied that the company would like to get 'rewards' from its customers not only for improved productivity, but also for other improvements of its tools, which means that ASML will stick to its value-based pricing model, but may adjust the pricing for the EXE:3800 model.

"We have always been able to show customers not just productivity upgrades, but also the value from better imaging, the value of better overlay, etc.," Dassen said. [But] you got this very strong correlation between throughput improvements and ASP. That is just the way things panned out, which, put in another way, customers were paying for the productivity upgrade, and the value that we gave them for free was the value associated with, let us say, overlay improvement, imaging quality […]. In the current environment, with the value that we bring, we are also having conversations with customers on how we get rewarded for that additional value."

TSMC's backlash against the price hikes

As ASML will likely not be able to hike prices on EUV tools that have already been pre-ordered and which are set to be delivered in the course of the next two years, existing chipmakers like TSMC will not feel the effects of the price increase at least over the next 24 months. Of course, if ASML adjusts prices of its EXE:3800-series scanners due to ship in 2028 – 2028, nobody is going to be happy. And yet, TSMC seems to be so upset that the sentiment has made it to the press. There are several reasons behind the reported backlash, but the major one seems to be strategic.

For years, TSMC has said that ASML's High-NA EUV lithography tools were too expensive, and that the company's engineers can continue innovating using Low-NA EUV systems. Also, adopting all-new High-NA EUV scanners will not be an easy undertaking in general, as the transition also requires new photoresists, photomasks, pellicles, metrology equipment, design rules, computational lithography flows, and numerous other supporting technologies and process innovations.

TSMC's mid-term expansion strategy, as well as a leading-edge roadmap through 2030, has been built around extracting more performance and resolution from conventional Low-NA EUV scanners using techniques such as improved masks, computational lithography, and multi-patterning where necessary. If ASML proceeds with its price hikes for Low-NA EUV tools, this can seriously hit one of the key economic foundations of TSMC's strategy.

TSMC's intention to avoid the usage of High-NA EUV scanners until at least 10A-class (1nm) process technology has an important economic advantage. A High-NA EUV system costs more than €350 million, whereas Low-NA systems are substantially cheaper. As a result, TSMC can choose its own trade-off between additional process steps and buying much more expensive lithography equipment. In contrast, Intel, which is set to adopt High-NA EUV lithography for its 14A fabrication process, has much less flexibility: If a particular process technology is designed around High-NA EUV layers, these extremely expensive scanners, along with other ingredients, become part of the manufacturing flow and affect wafer pricing.

One of the reasons TSMC would like to extend usage of Low-NA EUV systems is that it already has the world's largest install base of these tools, as well as mature processes, established flows, and plenty of innovations that enable it to stay ahead of the competition. However, if ASML systematically ties productivity improvements of each new Low-NA EUV generation to higher prices, the cost advantage of staying with Low-NA EUV gradually narrows, which greatly undermines TSMC's strategy.

There are several other reasons for TSMC to be particularly unhappy with ASML. Firstly, TSMC needs an enormous number of tools for its upcoming fabs in Taiwan, the U.S., and Japan. All of the company's leading-edge process technologies through 2029 rely on Low-NA EUV production tools. Even a relatively modest percentage increase applied to dozens of Low-NA EUV scanners can add billions of dollars to the company's capital expenditure (CapEx).

Secondly, ASML is essentially arguing that it deserves a share of its customers' improved economics. From TSMC's perspective, potential price adjustments are very different from charging more because a new scanner is materially more expensive to manufacture. ASML is effectively saying: 'Your fabs are more profitable, and our tools are more productive, therefore we want a piece of that.'

Thirdly, pricing negotiated today determines pricing and TSMC's economy for years to come. Now that ASML is sold out for 2027 and a significant part of 2028, it is negotiating terms for the second half of 2028 and onwards. Accepting a substantial increase now will inevitably carry through to dozens or hundreds of future Low-NA EUV systems, which directly affects TSMC's economics.

TSMC's A14 (1.4nm-class) fabrication process has made rapid progress in the last three months and is well ahead of N2 at the same stage of development, according to the company's update provided at its earnings call this week. The technology also faces strong customer interest and engagement across both smartphone and AI/HPC applications.

"A14 technology development is on track and progressing well. Internal product-like vehicle demonstrated close to 90% device performance and close to 90% 256Mb SRAM yield," said C.C. Wei, chief executive of TSMC, during the earnings call with analysts and investors.

A14 — which is expected to enter mass production in 2H 2028 — is making rapid progress in terms of performance and yield improvements. This April, the company disclosed that the production node achieved >85% target transistor performance and >80% 256Mb SRAM yield. Roughly three months later, both figures are approaching 90%, which suggests a gain of around 5% in device performance and nearly 10% in SRAM yield.

For comparison, TSMC's N2 demonstrated more than 80% of its target device performance and over 50% yield on a 256Mb SRAM test chip in April 2023. By April 2024, the process had advanced to more than 90% of its target device performance and over 80% SRAM yield. While development trajectories are not directly comparable, the figures suggest that A14 is maturing considerably faster than N2 did at a similar stage of development.

The very rapid progress of A14 compared to the relatively slow maturation of N2 at similar stages of development can probably be attributed, at least in part, to TSMC's growing experience with gate-all-around (GAA) nanosheet transistors. Back in 2023, the company barely had enough experience with the production of gate-all-around (GAA) nanosheet transistors, as N2 is its first process technology to adopt such a structure. By contrast, A14 relies on TSMC's 2nd Generation of GAA devices, so it can probably benefit from the transistor-design improvements, process refinements, and manufacturing expertise accumulated during the development and ramp of N2.

It appears TSMC has likely eliminated many of the yield limiters with A14 and N2, though keep in mind that a high 256Mb SRAM yield merely indicates low enough defect density and good process uniformity across a highly repetitive test structure, but it is not directly representative of functional or parametric yield of a commercial processor.

Nonetheless, the close to 90% device performance and close to 90% 256Mb SRAM yield about 2.5 years away from expected mass production start put TSMC's A14 progress well ahead of N2. Such progress can potentially enable TSMC to start high-volume manufacturing (HVM) using A14 ahead of schedule, provided that customer designs are ready, or initiate HVM with better-than-usual functional and parametric yields.

Speaking of customer design readiness, Wei indicated that clients strive to tape-out their A14 designs ahead of schedule, which is a good sign. It is also interesting to note that despite the fact that A14 lacks Super Power Rail backside power delivery (A12 will gain SPR in 2H 2019), it is set to be adopted not only by client processors, but also by AI/HPC applications.

"We are observing a strong level of customer interest and engagement on both smartphone and HPC/AI applications, and customer new tap-out activity is ongoing and ahead of schedule," Wei said.

A14 is TSMC's next-generation process technology that combines the company's 2nd Generation GAA nanosheet transistors with a new standard-cell architecture to improve performance, power efficiency, and transistor density. Compared with N2, TSMC expects A14 to deliver a 10% – 15% performance uplift at the same power and transistor count, or reduce power consumption by 25%–30% at the same frequency and complexity. The node is also projected to increase transistor density by around 20% for mixed designs and by 23% for logic.

As the semiconductor industry increasingly relies on ASML's EUV lithography tools both for logic and memory production, ASML is considering increasing prices of these systems as they deliver greater productivity and better value for its customers. However, with 2027 production nearly sold out and substantial 2028 orders already booked, meaningful increases may primarily affect systems delivered from late 2028 onward. Nonetheless, the idea has already angered TSMC, ASML's largest client, reports The Information.

"When it comes to Low-NA [EUV tools] pricing, of course, you know that we keep on increasing the productivity of the Low-NA tool, [which] gives us a pretty strong runway for potential price improvements going forward," said Roger Dassen, chief financial officer of ASML, during the company's quarterly earnings call. "Given the long order lead times that we have, that... doesn't translate into pricing effects tomorrow."

Value-based pricing set to persist… in a new way

ASML has long followed what it calls value-based pricing and gradually increased its quotes based on output, patterning costs, power consumption, and other benefits its new tools offer to clients.

Usually, this involved increasing prices once in a while. For example, if early Twinscan NXE Low-NA EUV systems cost roughly €100 million – €120 million ($115 million–$137 million), the more advanced are priced starting at €170 million ($195 million. It is still well below rumored quotes for High-NA EXE scanners that exceed €350 million ($400 million). At the same time, Low-NA productivity has risen from 160–170 wafers per hour (WPH) and ≤1.1nm matched-machine overlay to 220 WPH/260 WPH with NXE:3800E/NXE:3800F at 0.9nm. Future NXE:4200G/NXE:4200H systems are expected to exceed 300 WPH and improve overlay to ≤0.8nm–≤0.7nm.

"Clearly, the environment that we live in today, with the value that our products bring to customer — it's substantial— of course, gives us flexibility on pricing, more so than what you would have seen in the past," Dassen said. "Of course, we are executing on that as well."

However, later during the call, Dassen emphasized that ASML intends to maintain its value-based approach even in the current environment of high demand and limited supply in the semiconductor world. Yet, he stressed that from now on, ASML might want to charge for things beyond just productivity.

"We have always been able to show customers not just productivity upgrades, but also the value from better imaging, the value of better overlay, etc.," Dassen said. "[But] you got this very strong correlation between throughput improvements and ASP. That is just the way things panned out," he said, suggesting that ASML shares value with its clients.

No price hikes in the short term

ASML will be unable to hike prices of Low-NA EUV systems for another couple of years. Since orders that are in ASML's backlog already carry a sales value, subject to inflation adjustments, prices for much of the 2027 and early 2028 output may already be contractually determined. Unless existing contracts can be renegotiated, higher pricing could therefore primarily apply to 2028 shipments and beyond, or for new orders that somehow get squeezed in in 2027. The NXE:4200G, due in 2029, should naturally lift average selling prices anyway as it gets major performance improvements.

TSMC is upset

For TSMC, however, the issue is strategic. The foundry's leading-edge roadmap through 2030 relies on extending Low-NA EUV with better masks, computational lithography, and multipatterning. Until then, TSMC's strategy has always been avoiding High-NA EUV until at least its 10A-class (1 nm-class) technology. If ASML hikes prices of its future Low-NA EUV lithography systems, it will likely affect all of TSMC's plans for the next several years.

TSMC already operates the world's largest Low-NA EUV fleet and needs many more scanners for fabs in Taiwan, the U.S., and Japan as it executes its global expansion strategy. Consequently, even modest increases beyond TSMC's projections could add billions to capital spending, reduce the economic advantage of postponing High-NA, and ultimately raise its manufacturing costs. Moreover, accepting higher prices now could establish the baseline for dozens or hundreds of future systems, which will allow ASML to capture a larger share of the economic value created by increasingly productive lithography equipment.

Can this force TSMC to transition to High-NA EUV tools earlier than planned? Moving to High-NA EUV requires not only €350-million-plus scanners but also new resists, masks, pellicles, metrology, design rules, and computational lithography flows, which are likely not ready at TSMC.

Tower Semiconductor has announced a dual-track expansion of its 300mm silicon photonics, silicon germanium, and advanced packaging operations in Japan, committing up to $3 billion net of grants with backing from the country's Ministry of Economy, Trade and Industry (METI). Alongside the announcement, the Israeli specialty foundry raised its 2028 business model to approximately $3.6 billion in revenue and $1.2 billion in net profit, and it says those targets rest entirely on the first of the plan's two tracks: reviving the shuttered Arai fab it inherited from Panasonic and maximizing its running 300mm fab in Uozu, Toyama Prefecture.

Two tracks, one committed

Track One converts the former Arai facility, designated Fab 6, into a 300mm silicon photonics and advanced optical packaging plant while expanding output at Fab 7 in Uozu, with full production readiness expected during the fourth quarter of 2027. The Arai plant ceased operations in July 2022 because it exclusively served Nuvoton Technology Corporation Japan (NTCJ) rather than Tower's foundry customers, according to Tower's SEC filings, leaving an intact fab shell sitting idle for four years.

Track Two calls for constructing a new 300mm fab adjacent to Fab 7, which Tower says would deliver a multi-fold increase in silicon photonics and silicon germanium capacity and become "highly accretive beginning in 2029." The company hasn't signed definitive agreements for it, however, and none of the new 2028 targets depend on it.

A restructuring of the TPSCo joint venture, announced in March 2026, cleared the way for all this. Tower entered Japan in 2014 by buying 51% of Panasonic's three-fab semiconductor manufacturing operation, and Panasonic sold its remaining stake to Nuvoton in 2020. Under the March agreement, Tower takes full ownership of the 300mm Fab 7, while NTCJ absorbs the 200mm operations and pays Tower $25 million, with closing expected on April 1, 2027. Sole ownership of Fab 7 removed the joint-venture structure that would have complicated a $3 billion buildout.

Tower CEO Russell Ellwanger contrasted the approach with greenfield construction and fab acquisitions, which he said typically require years of process development, customer qualification, and financial stabilization while ramping from zero revenue against high fixed costs. Reusing a dormant building next to a qualified, cash-generating photonics fab is why Tower can achieve production readiness roughly 18 months ahead; Rapidus, by comparison, broke ground on its greenfield Chitose site in September 2023 and doesn't expect mass production until 2027.

29% increase in revenue

Tower reported $1.566 billion in revenue and $220 million in net profit for 2025, up from $1.436 billion and $208 million in 2024. The new 2028 model more than doubles 2025 revenue and implies a net margin of around 33%, against roughly 14% today. Measured against the prior 2028 model of $2.8 billion in revenue and $750 million in net profit, which Tower reaffirmed in its Q1 2026 report in May, the new targets add 29% to revenue and 60% to net profit.

Silicon photonics revenue is doing most of the heavy lifting, with Ellwanger telling analysts on the company's Q4 2025 earnings call in February that silicon photonics revenue reached $228 million in 2025, up from $106 million in 2024, and hit a $380 million annualized run rate in the fourth quarter, a figure he noted includes some non-wafer engineering revenue. In May, Tower disclosed $1.3 billion in contracted silicon photonics revenue for 2027 from its largest customers, backed by $290 million in prepayments already collected.

Tower's photonics customer roster includes Innolight, which builds 400G, 800G, and 1.6T optical transceivers on Tower's PH18 platform family, and Marvell, which said in June it had shipped more than five million coherent photonic ICs manufactured with Tower. The company claims more than 50 active silicon photonics customers and supplies foundry capacity for 200 Gb/s-per-lane devices used in 1.6T transceivers.

Tower's forward-looking disclosures flag construction delays, equipment lead times, permitting, and METI grant covenants that "may result in loss of a portion or all of the grant funds." The implied margin expansion also assumes sustained AI and data center optics demand from a concentrated group of very large customers through 2028, a dependency Tower acknowledges.

Tower’s position in the photonics foundry race

GlobalFoundries paid $453 million in cash for Singapore's Advanced Micro Foundry in November 2025, according to its annual report, a deal the company said made it one of the largest silicon photonics manufacturers. TSMC's COUPE co-packaged optics platform is tracking Nvidia's optical interconnect roadmap, with 1.6 Tb/s optical engines arriving in 2026 products.

Tower occupies a different lane from TSMC, as a merchant foundry serving dozens of transceiver makers and chip designers, rather than a packaging platform aligned with one customer's rack-scale plans. GlobalFoundries competes with Tower far more directly, and the two are also in court, with GlobalFoundries pursuing patent infringement claims against Tower.

MarketsandMarkets estimates the silicon photonics market at $2.65 billion in 2025, growing to $9.65 billion by 2030 at a 29.5% compound annual growth rate. Demand for optical data movement in AI clusters underpins those forecasts, as interconnects shift from copper to light at 800G and 1.6T speeds.

METI's support for Tower joins a Japanese subsidy program that has committed up to ¥1.2 trillion to TSMC's JASM fabs in Kumamoto, roughly ¥536 billion to Micron's Hiroshima operations, and around ¥2.9 trillion in planned funding for Rapidus. Tower's award appears to be the program's first at this scale for a dedicated silicon photonics foundry.

Intel agreed to buy Tower for $5.4 billion in 2022, but abandoned the deal in August 2023 after Chinese regulators declined to approve it, paying Tower a $353 million termination fee. The Japan program is the largest capital commitment in Tower's history, well beyond the up-to-$300 million arrangement it struck with Intel in September 2023 for 300mm capacity in New Mexico. Three years after nearly becoming an Intel subsidiary, Tower is building its own flagship instead.

Intel has entered high-volume manufacturing using ASML's High NA extreme ultraviolet (EUV) lithography technology for a subset of its Intel Core Ultra Series 3 "Panther Lake" processors, becoming the first company to ship high-volume logic products manufactured with the technology. ASML announced the milestone in an official press release on Wednesday, July 15, confirming that Intel Foundry is running the qualified High NA layers on its Intel 18A process node in Oregon.

According to ASML, Intel is using High NA EUV to pattern selected Intel 18A layers, with products already shipping to customers at yields matched to those achieved on ASML's existing NXE EUV platform. These layers are dual-qualified, meaning the same layer can be exposed on either an existing 0.33 NA NXE scanner or a 0.55 NA EXE scanner, with the resulting wafers being interchangeable.

High NA EUV has long been viewed as the successor to today's EUV lithography, promising to extend semiconductor scaling by enabling manufacturers to print smaller, denser circuit patterns that are becoming difficult to achieve with existing tools. Until now, the platform had been confined to R&D work. ASML’s announcement marks the first time High NA EUV has been used to produce and ship a high-volume commercial logic product.

Panther Lake, built on the Intel 18A manufacturing process, is spearheading this transition. Rather than replacing the company's entire lithography flow, Intel is applying High NA EUV to specific layers while the remainder of the chip continues to be manufactured using conventional lithography.

High NA EUV builds on the same 13.5-nanometer extreme ultraviolet light used by today's scanners but increases the optical system's numerical aperture (NA) — how much light a lens system can collect and focus onto a silicon wafer — from 0.33 to 0.55. The higher value resolves finer features in a single exposure, allowing chipmakers to print smaller patterns with greater precision and process control.

This increased resolution is expected to reduce reliance on complex multi-patterning techniques for some of the industry's most demanding layers, thereby simplifying manufacturing and improving feature fidelity. In the long term, these capabilities are expected to support higher transistor densities and improved performance in future processors, particularly as AI workloads continue driving demand for increasingly advanced semiconductor technologies.

"With increased resolution and better process control, the introduction of High NA EUV marks a substantial development in semiconductor lithography," said ASML President and CEO Christophe Fouquet. "We are proud to play a role in enabling the smaller, denser patterning that will accelerate advancements in AI and other emerging technologies."

Intel and ASML have been working towards this milestone for several years. In 2024, Intel completed installation of one of the industry's first commercial High NA EUV lithography systems, the TWINSCAN EXE:5000, at its Hillsboro, Oregon, research and development facility. The company later became the first to qualify ASML's second-generation TWINSCAN EXE:5200B, which increases wafer throughput and overlay accuracy while incorporating an improved EUV light source over its predecessor.

While the announcement represents High NA EUV's commercial debut, it does not mean Panther Lake is manufactured entirely using the new lithography platform. Instead, Intel has qualified High NA for selected layers, an approach that mirrors how new lithography generations are typically introduced into advanced semiconductor production before broader adoption across future nodes.

Intel Foundry Executive Vice President and General Manager Naga Chandrasekaran said that qualifying the High NA process option on selected Intel 18A product layers enables the company's existing tool fleet to deliver higher manufacturing output while providing flexibility for future process technologies.

Panther Lake itself is not a future product. Intel launched Core Ultra Series 3 at CES on January 5, 2026, opened preorders the following day, and put systems on shelves globally from January 27. The Core Ultra X9 378H followed in April alongside the value-tier Core Series 3, code-named Wildcat Lake, and the handheld-focused Arc G3 parts arrived on May 28.

The announcement’s statement that the product is shipping to customers refers to wafer flow from the fab into the supply chain, rather than to a product launch. ASML says the two companies will continue working on High NA readiness, with the flexibility to incorporate the technology into future nodes based on customer needs — most immediately, Intel 14A, which Intel has designed to use High NA on a set of its tightest-pitch layers.

Google plans to use Intel's EMIB-T packaging for its next-generation TPU codenamed Humufish, according to SemiAnalysis. TSMC's portfolio of chip-on-wafer-on-substrate (CoWoS) technologies has become the de facto standard advanced packaging option for nearly all AI and HPC processors made in the industry. Competing offerings are usually considered as secondary solutions if CoWoS is in tight supply, but things are beginning to change.

Google is a long-standing CoWoS customer for TPUs, starting from the Third-Generation TPU, all the way to Google's latest Eighth-Generation TPUs. Assuming that SemiAnalysis's report about Google's decision to move to EMIB-T with its Ninth-Generation TPUs is accurate, it's a big decision for Google, as switching from one advanced packaging technology to another is a complicated endeavor, which involves plenty of changes and unknowns. Understanding Google's reasons for the switch could shed some light on the prospects of Intel's and TSMC's advanced packaging technologies, which will be used by leading chip designers and hyperscalers in the coming years.

Advanced packaging technologies at glance

For years, Google used TSMC's CoWoS-S, and later, CoWoS-L packaging. Initially, the company used CoWoS-S packaging, which relies on a silicon interposer up to 3.3X the reticle size, but with its 7th- and 8th-Generation TPUs, the company moved to CoWoS-L. CoWoS-L relies on a redistribution layer (RDL) interposer with embedded local silicon interconnect (LSI) bridges that enable high-performance die-to-die links, which can scale packages to 5.5X the reticle size today. TSMC promises to improve CoWoS-L's capabilities to scale over 14X the reticle size by the end of the decade.

Unlike CoWoS, Intel's embedded multi-die interconnect bridge (EMIB) technology does not use any interposers. The technology instead relies on tiny embedded silicon bridges within the substrate to enable high-density die-to-die interconnections, whereas everything else is routed through an inexpensive organic substrate.

EMIB-T adds through-silicon vias (TSVs) to the bridge, which enables power to flow vertically instead of going through the organic substrate. In addition, Intel's EMIB-T also integrates sophisticated metal-insulator-metal (MIM) capacitors and a dedicated ground plane into the bridge to improve power integrity. The latter is a particularly important feature of complex next-generation AI accelerators, which demand more, cleaner power, and for which power delivery is becoming as challenging as signal routing.

The main selling point of EMIB (and EMIB-T) is that it is not constrained by interposer reticle limits as it places small silicon bridges only where high-density die-to-die links are needed. Strictly speaking, CoWoS-L is not either, as it uses LSIs locally as well. The difference is that those bridges are embedded into a package-wide RDL interposer that connects everything and enables dense interconnections across the package.

Since both CoWoS-L and EMIB-T are designed to address the same applications and have many similarities in the way they do this, the choice between them is likely driven by a combination of factors rather than one single advantage or disadvantage. On the technology side of matters, these factors include interconnect performance and density, power delivery, scaling beyond very large package sizes, and mechanical rigidity. On the business side of things, costs, capacity availability, and supply chain diversification are also a significant factor.

Crucial differences

SemiAnalysis claims that the main advantage of EMIB/EMIB-T over CoWoS is the lack of reticle limit, but this argument does not fully hold against CoWoS-L, as it was invented specifically to escape the reticle limitation by replacing the monolithic silicon interposer with localized LSI bridges.

When it comes to dense, package-wide routing, CoWoS-L's RDL interposer is fundamentally superior to an ordinary organic substrate offered by EMIB-T. Organic substrate wiring has coarser line/space dimensions and larger vias, so it cannot provide the same routing density as CoWoS-L's fine-pitch RDL. Where an EMIB bridge connects adjacent dies, Intel can achieve very high interconnect density. But anything that needs to travel beyond those bridges must use the package substrate or cross a topology involving additional bridges.

By contrast, CoWoS-L gives the designer two levels of connectivity: LSIs provide extremely dense local die-to-die connections, while the global RDL interposer provides relatively dense and flexible routing across the entire package. This means the RDL can carry longer, lower-density connections without consuming valuable LSI resources, while still offering much finer routing than the underlying package substrate.

One scenario for Google's choice is that it potentially wanted better power delivery than what CoWoS-L could offer. EMIB-T integrates TSVs for vertical power delivery, sophisticated MIM capacitors for local decoupling, and a dedicated ground plane into its silicon bridges. The combination of these features substantially reduces power-delivery impedance and improves transient response and power integrity, which gives EMIB-T a major advantage over conventional EMIB for power-hungry AI accelerators. However, we have no idea how EMIB-T stacks up against CoWoS-L in the case of Google’s Humufish.

Of course, the larger the RDL interposer becomes, the greater its parasitics can become, potentially limiting scaling unless TSMC finds ways to mitigate them. However, EMIB does not eliminate long-distance wiring: If two distant dies must communicate, those signals still have to travel somewhere, and routing them through an organic substrate is not inherently electrically superior to routing them through a purpose-built RDL interposer. Therefore, it is difficult to claim that Google chose EMIB-T over CoWoS-L, simply because EMIB-T offers superior package-wide electrical characteristics.

After Nvidia suffered yield loss with its Blackwell data center GPUs due to an alleged mismatch in the coefficient of thermal expansion (CTE) among the GPU chiplets, LSI bridges, RDL interposer, and motherboard substrate, which led to warping and system failure, it is reasonable to question the mechanical rigidity of CoWoS-L packages. Nvidia has found a solution for its dual compute chiplet Blackwell packages, and so have other developers of AI accelerators. However, as package dimensions increase, they may behave differently, therefore causing yield losses.

By contrast, EMIB/EMIB-T eliminates the large RDL interposer and embeds small silicon bridges in the organic substrate, so most of the package consists of the substrate itself. This does not make EMIB/EMIB-T packages immune to mechanical failures, as large packages can warp and bend, causing various problems. However, as such packages lack the very source of global thermomechanical stress, they can potentially be more robust mechanically. However, EMIB-T can potentially complicate things because TSVs, additional metal structures, MIM capacitors, and their ground plane make the bridge more complex. Thus, Intel must manage both global package warpage and local stresses around each embedded bridge to ensure the mechanical rigidity of these packages.

Ironically, while CoWoS-L can offer denser package-wide routing, which is better for ultra-large processors, EMIB-T may potentially provide better mechanical rigidity required for such devices. Nonetheless, EMIB-T and its organic substrate do not eliminate package bending or cracking risks entirely.

Economics

If Google's Humufish TPU really moves to EMIB-T, the decision could well be both technical and strategic. Google has the engineering resources to opt for an all-new packaging technology in an effort to lower costs and eliminate dependence on TSMC's constrained CoWoS capacity. Nvidia tends to procure advanced packaging allocations years in advance, so it is possible that Google could simply not get enough CoWoS-L wafers for its 9th-generation TPU.

As a bonus, Google can also build relationships with Intel Foundry without using the company's fabrication technologies. In fact, keeping in mind that Intel and Google already have a strategic agreement covering Intel Xeon CPUs, it wouldn't be too surprising to learn that the cloud giant is courting Intel Foundry as well.

Both Intel's EMIB-T and TSMC's CoWoS-L have their own technological and economic advantages and disadvantages. Perhaps the biggest advantage of CoWoS-L is its predictability, as the company has experience with that tech. However, if Google has decided to drop that predictability in favor of an all-new packaging method, it may well have a combination of technological and strategic reasons to do so.

Researchers from Osaka Metropolitan University have developed a programmable thermal device that can control where heat is radiated while remembering its configuration even after power is removed, a capability that could one day contribute to smarter thermal management in high-performance chips, silicon photonics, infrared sensors, and energy-harvesting systems. The work, published in Laser & Photonics Reviews, overcomes two longstanding obstacles that have prevented the practical realization of nonreciprocal thermal devices.

The device combines a magneto-optical material — a material that changes its optical properties in the presence of a magnetic field — with a phase-change material known as germanium-antimony-tellurium (GST) to independently control how a surface absorbs and emits infrared radiation. Unlike previous designs that lost their functionality once power was removed or only worked when light struck the surface at extreme angles, the researchers say their device operates almost straight on while retaining its programmed state without continuous energy input.

Under normal circumstances, materials follow a principle stating that if a surface efficiently absorbs heat at a particular wavelength and direction, it must also emit heat equally well under the same conditions. This relationship, defined by Kirchhoff's law of thermal radiation, holds for conventional materials and limits how precisely engineers can manipulate heat. Rather than directing thermal energy where it is most useful, these materials simply emit heat based on how they absorb it.

Circumventing this relationship has become an active area of research, as it could give engineers an entirely new way to control thermal energy. Devices capable of independently steering absorption and emission could improve radiative cooling, thermophotovoltaic systems that convert heat into electricity, infrared sensing, thermal communication, and other photonic technologies where controlling heat is just as important as controlling light.

Researchers have explored several ways to achieve this by breaking Lorentz reciprocity, the physical principle that links incoming and outgoing electromagnetic waves. Most approaches rely on magneto-optical materials, magnetic Weyl semimetals, or actively modulated metasurfaces. However, these designs have generally encountered two major problems. First, they require light to strike the surface at very oblique, or grazing, angles to produce strong directional behavior. While this works experimentally, it significantly reduces the amount of usable thermal radiation and produces broad, inefficient emission patterns. Second, many existing designs are volatile. Their behavior disappears as soon as the magnetic field, electrical signal, or heating source controlling them is removed, making continuous power necessary simply to maintain their operating state.

The Osaka Metropolitan University team tackled both limitations by combining two materials that perform complementary roles. The first is indium arsenide (InAs), a magneto-optical semiconductor whose interaction with infrared light changes in the presence of a magnetic field. Rather than allowing light to behave identically in all directions, the material introduces a directional asymmetry that enables nonreciprocal thermal behavior. The second ingredient is GST, a phase-change material that can reversibly switch between amorphous and crystalline states, dramatically changing its optical properties while retaining whichever state it is written into, even after power is removed.

The researchers patterned GST into a microscopic grating above the InAs layer, forming what they describe as a magneto-optical metagrating. The InAs provides the directional control needed to separate heat absorption from heat emission, while the GST layer acts as a non-volatile switch that stores the device's operating mode. Applying a magnetic field tunes how infrared radiation interacts with the structure, while changing the phase of the GST permanently alters that behavior until it is intentionally rewritten. In effect, the device can be programmed to emit heat differently and retain that configuration without requiring continuous energy.

According to the researchers, the prototype achieved a nonreciprocity factor approaching 0.9 while operating at an incidence angle of just three degrees, much closer to normal incidence than the steep angles typically required by previous designs. The system also supports continuous tuning via changes in the magnetic field or incident angle, as well as digital on-off switching via the GST phase transition. The team further analyzed why the nonreciprocal effect weakens when GST changes state, concluding that the reduction results from a combination of optical field redistribution and increased damping rather than simple absorption losses alone.

Although the technology remains an early-stage research demonstration, the ability to program thermal radiation could eventually become valuable in computing hardware as processors continue to pack more transistors, chiplets, and photonic components into increasingly compact packages. Future thermal metasurfaces could give engineers another tool for directing heat away from hotspots, reducing thermal interference between neighboring chiplets, or stabilizing silicon photonic devices whose optical characteristics shift with temperature.

Beyond computing, the researchers also envision applications in radiative cooling, thermophotovoltaic energy conversion, infrared emitters, thermal communication systems, and photonic memory technologies. For now, however, the work remains a laboratory demonstration rather than a deployable technology. Considerable engineering challenges remain before programmable thermal emitters find their way into commercial electronics.

Micron committed up to $3 billion to the U.S. semiconductor supply chain last week. Of that, $500 million goes to GlobalWafers as strategic financing — subject to definitive agreements and closing conditions — for its 300mm raw silicon wafer plant in Sherman, Texas, and the two companies will sign a 10-year agreement for access to that plant's output. Ben Tessone, Micron's senior vice president and chief procurement officer, tied the move to securing "critical input materials." In a second announcement from Boise the same day, Micron raised its planned US spending to more than $250 billion through 2035, up from $200 billion, and poured the first load of concrete at its Clay, New York megafab a quarter ahead of schedule.

Running until 2035, the $250 billion spending target is attached to a goal of making 40% of Micron's DRAM in the U.S. by the mid-2030s. Only a relatively paltry $500 million of that $250 billion has been earmarked for buying wafer supply from GlobalFoundries, the only U.S. supplier that’s capable of producing 300mm wafers.

The 300mm wafer market

Roughly 85% of global 300mm wafer capacity sits with five suppliers, according to market research firm Mordor Intelligence: Shin-Etsu and SUMCO of Japan, Taiwan's GlobalWafers, Germany's Siltronic, and South Korea's SK Siltron. The two Japanese firms hold more than half between them.

GlobalWafers America opened the Sherman plant in May last year on an initial $3.5 billion investment. It’s the first fully integrated 300mm raw wafer facility built in the U.S. in more than two decades, and the company says it’s the only CHIPS-participating supplier capable of producing advanced 300mm wafers domestically. The site holds a CHIPS Act award of up to $406 million, finalized in December 2024 and shared with a silicon-on-insulator plant in St. Peters, Missouri. Commerce Department figures from 2022 put full-build capacity at around 1.2 million wafers per month across a six-phase campus, with one phase currently running.

Meanwhile, SUMCO is ending 200mm production at its Miyazaki site and has slowed new 300mm expansion. The leading-edge capacity Shin-Etsu and SUMCO added in 2025 was sized to match contracted demand rather than to build ahead of the market. Wafer suppliers have run this way for a decade, protecting margins instead of chasing volume, and with suppliers holding back, the capital for new capacity increasingly comes from their customers.

GlobalWafers chairperson and CEO Doris Hsu set out her terms for that at the Sherman opening, announcing an additional $4 billion for the site and telling Reuters that further phases depended on the first two turning a profit, on customers signing long-term contracts, and on reasonable pricing, prepayments, and government support. Micron's $500 million in financing and a decade-long supply commitment cover most of that list, and Hsu has since called the Micron agreement the largest long-term deal in her company's history and said a second Sherman phase is now necessary.

Micron is locking in its own customers on the same basis, having signed a strategic customer agreement with General Motors on July 1 and another with Ford on July 6, two of 16 such agreements the company cited on its fiscal Q3 2026 earnings call. Each ties future memory output to a named buyer.

We’ve seen the industry do this before. During the memory boom of 2017-2018, chipmakers signed prepaid, take-or-pay wafer agreements to guarantee supply, but those prepayments became balance-sheet liabilities when DRAM pricing fell through 2019. SK Group chairman Chey Tae-won told an audience at Nvidia's GTC conference that the current wafer shortage could last through 2030 with a deficit above 20%, which is the argument for signing now. Conversely, the 2019 write-downs are the argument against.

HBM packaging

High-bandwidth memory is of course the component that’s currently carrying the steepest premiums in the AI market, and a fabbed wafer isn’t yet HBM. The die has to be stacked and packaged using advanced 2.5D methods with through-silicon vias, the capacity for which is located almost entirely in Asia. Micron's committed HBM packaging anchor is a roughly $7 billion facility in Singapore, with operations starting in 2026. Per a June 2025 SEC filing, the company lists U.S. HBM packaging as an intention, but no committed site or date has yet been announced.

As for U.S. packaging capacity that is scheduled, it’s all clustered in or around 2028. SK hynix is building the first U.S. 2.5D advanced packaging plant in West Lafayette, Indiana, a roughly $3.87 billion project with mass production set for the second half of 2028. Amkor, meanwhile, has expanded its Peoria, Arizona campus to $7 billion, with production slated for early 2028. TSMC's Arizona fabs run leading-edge logic but don’t yet offer high-volume 2.5D packaging on U.S. soil — this is reportedly planned for 2029. While it’s true that a wafer fabbed in New York and packaged in Singapore counts toward domestic DRAM, it doesn’t make the finished HBM stack domestic.

Output timelines vs. 2035

Micron's Manassas, Virginia fab began producing 1-alpha DRAM in May, and it’s the only U.S.-made memory in volume, representing roughly 2% of the world’s supply. The first new Idaho fab should reach wafer output in mid-2027, and the second in late 2028, while the Clay, New York campus isn’t expected to produce until around 2030. The $250 billion capex figure runs five years past that, while conventional DRAM contract prices continue to rise at record amounts — more than 90% quarter over quarter in early 2026, according to TrendForce — and manufacturers increase prices. Apple raised MacBook, iPad, and Vision Pro prices last month, citing memory costs, and none of the announced U.S. capacity will do anything to alleviate such shortages.

Samsung and SK hynix committed a combined $880 billion under a South Korean government-coordinated chip and AI program announced last month, spread over roughly a decade. That spending is domestic to Korea and separate from Samsung's $37 billion Texas footprint. But set next to Micron's $250 billion, we’re seeing a pattern of more companies announcing more capex than construction projects can physically absorb.

HBM consumes roughly three times the wafer area per bit of standard DDR5, so shifting production to HBM removes more commodity memory from the market. DRAM already takes around a fifth of global 300mm capacity, and memory is the largest single application for 300mm silicon. Micron's Sumit Sadana told CNBC in January the company could meet “at most” two-thirds of some customers' medium-term demand.

Intel has unveiled Starfire, a space-grade system-on-chip designed for the U.S. government that pairs eight CPU cores and a three-tile NPU built on its Intel 18A node with an Intel 3 graphics tile, all in one Foveros package. Intel published the Starfire sell sheet, listing two versions that draw 10 W and 35 W and reach up to 45 and 75 TOPS, respectively, rated to run between -55 and 125 Celsius.

Both SKUs share the same layout of four Intel 18A P-cores, four low-power efficiency cores, a three-tile NPU also on 18A, and a four-core Xe GPU with 64 execution units built on Intel 3. The Low Power part runs its P-cores at 1.0 GHz, efficiency cores at 850 MHz, and the GPU between 800 MHz and 1.0 GHz. The Performance part clocks the P-cores to 3.1 GHz, efficiency cores to 2.1 GHz, and the GPU to 2.0 GHz. Both carry 12 PCIe Gen4 lanes, support LPDDR5 or DDR5, and are rated for a 10-plus year lifetime.

Intel builds the CPU and NPU on 18A and the GPU on the older Intel 3, the same node division it used for Clearwater Forest, the 288-core Xeon that stacks 18A compute tiles on Intel 3 base tiles. Smaller transistors hold less charge per stored bit, which makes leading-edge silicon more prone to radiation-induced bit flips, so committing 18A to orbit leans on RibbonFET and design-level hardening rather than a mature, inherently more tolerant node.

The market Starfire is targeting has run on BAE Systems' RAD750 for two decades. That radiation-hardened PowerPC part clocks 110 to 200 MHz, carries 10.4 million transistors, and is built on 150nm or 250nm lithography, per public specifications, and it flies on the Mars rovers, Kepler, and Fermi, among more than 150 spacecraft. BAE's multi-core RAD5545 and the Microchip-built processor NASA is developing to reach 100 times the throughput of current spaceflight chips are the more recent step up. Starfire's up to 75 TOPS and dedicated NPU put it in a different bracket, built for on-orbit AI inference rather than telemetry and control.

Intel lists the radiation data, covering total ionizing dose, single-event latch-up, and single-event effects, as characterization in process, so the part isn't radiation-qualified yet, and it notes the specs are subject to change. Intel Government Technologies is handling Starfire, with samples in Q3 2026 and a pitch of market-competitive pricing and domestic manufacturing. Intel Foundry is the only U.S.-based maker of leading-edge logic, holds Trusted Foundry status, and has tied its 18A and packaging roadmap to Pentagon programs including RAMP-C and SHIP, though 18A yields aren't expected to reach industry-standard levels until 2027.

Apple's planned M7 Ultra chip is being designed to support up to 1.5 TB of unified memory and to push AI performance toward the class of Nvidia's Blackwell accelerators, according to a new Bloomberg report published by Mark Gurman. But whether the lofty top memory config can ship at all will depend on the state of the memory market, and the part isn't expected until 2028. The same report says Apple has compressed its Mac silicon timeline, taping out the M7 roughly six months after the M6.

We've already heard that Apple plans to release a base M6 chip this fall for entry-level Macs, then skip the Pro, Max, and Ultra versions of that generation and move straight to the M7 line. However, Gurman now reckons that we'll see a base M7 in the first half of 2027, M7 Pro and M7 Max at the end of 2027, and the M7 Ultra in 2028. Apple reportedly began taping out the M7 about six months after it started the same process for the M6, which is what has enabled the company to pull the schedule forward.

The 1.5 TB target for the M7 Ultra is roughly twice the capacity Apple has planned for the M5 Ultra, per Gurman, who tied the configuration directly to memory availability. Apple already pulled the 128GB Mac Studio this year over supply constraints as DRAM prices climbed, and a 1.5 TB part would call for far more of the same scarce, high-cost memory.

Apple's current M3 Ultra already reaches 819 GB/s of memory bandwidth by fusing two Max dies, and it's the Ultra tier, not the base chips, that carries the heaviest local-AI workloads. Gurman describes the M7 Ultra as a large step up in AI performance rather than stated parity with Nvidia's data-center silicon. "I'm told the processor dramatically upgrades AI performance, bringing it closer to the class of dedicated AI accelerators such as Nvidia Corp.'s Blackwell," Gurman wrote in his report.

Apple is also preparing an AI server built on the M5 Ultra under the code name J246 for deployment soon, with a second server chip based on the M7 Ultra planned for 2029, according to the report. The 2028 generation, which includes an M8 chip code-named Soko and a high-end Mac part called Cardinal, moves to a 1.4nm process. That aligns with TSMC's A14 node, which the foundry has scheduled for mass production in the second half of 2028.

None of the dates or specifications have been confirmed by Apple.

SK hynix has completed the largest-ever foreign company IPO in U.S. history, raising $26.5 billion in its Nasdaq debut today, July 10. The South Korean memory giant sold 177.9 million American depositary receipts (ADRs) — a U.S.-listed stand-in for a foreign share — at $149 apiece, each representing a tenth of a Seoul-listed share. The offering was more than seven times oversubscribed and drew demand from more than 500 investment firms, according to Financial Times. Temporary Nasdaq trading is underway under the ticker SKHYV before regular-way trading begins as SKHY on Monday, July 13.

The offering was led by Bank of America, Citigroup, Goldman Sachs, and JPMorgan, with nine additional firms rounding out a 13-bank syndicate. Anchor demand came from heavyweight institutions including Baillie Gifford, Coatue Management, and Situational Awareness Partners, which together signaled interest in as much as $7 billion of stock, according to people familiar with the matter cited by Financial Times.

SK hynix is the world's leading maker of high-bandwidth memory (HBM), the vertically stacked DRAM that has become critical infrastructure for AI accelerators. The company has said it will steer the proceeds toward boosting its AI-memory manufacturing capacity. Confirmed build-outs include the first-phase fab at the massive Yongin semiconductor cluster, a new P&T7 advanced-packaging line in Cheongju, and EUV lithography equipment slated for delivery by the end of next year. Separately, SK hynix is constructing its first U.S. production site, a $4 billion advanced-packaging plant in West Lafayette, Indiana, targeted for completion around 2028. The facility is eligible for up to $458 million in CHIPS Act grants and up to $570 million in federal loans.

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SK hynix is seeing sensational growth thanks to the ongoing AI boom. The company is reportedly on track to post over 200 trillion won ($133 billion) in operating profit this year, a record-breaking figure that would see SK hynix employees earn around $400,000 each in bonuses. The company’s Seoul-listed stock is up roughly 220% year-to-date and has climbed more than sixfold over the past year.

In late June, SK hynix briefly surpassed Samsung as South Korea's most valuable company, closing at around 2,080 trillion won (about $1.35 trillion), a meteoric rise for a company that almost declared bankruptcy in 2001 and, more recently, recorded an annual operating loss of 7.73 trillion won in 2023. That rise doesn't seem like it will be slowing down any time soon. SK hynix has said its entire 2026 output of HBM, DRAM, and NAND is already sold out, with the crunch expected to extend into 2027.

Japanese chipmaker Rapidus will try to lure customers away from TSMC not only by offering a different kind of service, but also by offering its manufacturing services at lower prices, chief executive Atsuyoshi Koike announced this week. The company's plan to rival TSMC in terms of pricing appears on the surface as a risky move, as the company moves to develop leading-edge process technologies.

At present, Rapidus is looking at charging ¥3 million – ¥3.5 million ($18,550 - $21,635) per wafer processed using its 2nm-class fabrication process, which is significantly below TSMC's rumored quote of around $30,000 per N2 wafer, and is comparable to what Samsung is rumored to offer with its SF2 manufacturing technology, set at $20,000 per-wafer. Actual prices will depend on exchange rates, though Rapidus' general idea of offering significantly lower quotes than TSMC is immediately apparent.

Rapidus plans to start high-volume manufacturing (HVM) using its 2nm-class fabrication technology by the second half of 2027. The ramp of a new fab will take some time, so expect meaningful volumes from Rapidus to only be produced in 2028, when TSMC's N2 will no longer be its leading-edge node.

By the time Rapidus starts HVM at its IIM-1 in 2027, TSMC will have ramped production of chips using its performance-enhanced N2P manufacturing node, and the company will also absorb all the yield learning with gate-all-around the company will have with its N2 present at five fab modules. Furthermore, by the time Rapidus reaches meaningful volumes at IIM-1 in 2028, TSMC will have ramped up production using its advanced A16 fabrication process with Super Power Rail backside power delivery as well as a 3^rd-generation 2nm-class node named N2X.

In addition to the vast 2nm-capable capacity and process maturity that should be kept in mind when comparing Rapidus with TSMC, there is another factor to consider. One of TSMC's major advantages over its rivals is its Open Innovation Platform (OIP) ecosystem, which includes comprehensive electronic design automation tools, silicon-proven IPs, even for the latest nodes, a host of contract chip designers, and advanced packaging services not only from TSMC but also from its partners. For now, neither Rapidus nor Intel and Samsung Foundry can offer anything close to TSMC's OIP.

Given the advantages that TSMC will likely have over competitors with its 2nm-class fabrication technologies in 2028, lower pricing may be among the few ways to compete against the world's largest foundry. Rapidus' strategy of offering lower quotes while operating a single fab does not seem like the best way of earning money, but perhaps a certain way to lose it.

However, Rapidus may have another ace up its sleeve with single wafer processing across all process steps. The approach will greatly speed up the production cycle, which will be its indisputable advantage over other chipmakers, albeit at the cost of tool usage efficiency. Will lower quotes and shorter production cycles be enough for Rapidus to win customers from TSMC? Only time will tell.

Rapidus is reportedly negotiating with more than 60 potential customers, mainly overseas companies, which demonstrates the company's ambitions to become a viable rival to the global leader TSMC as well as contract chipmakers Intel Foundry and Samsung Foundry.

Researchers in Korea and Japan have presented two separate memory-integration proposals that aim to increase HBM (High-Bandwidth Memory) capacity and bandwidth without trapping more heat inside ever-taller DRAM (Dynamic Random Access Memory) stacks, one of the most pressing challenges facing future AI accelerators. Presented at the 2026 IEEE/JSAP Symposium on VLSI Technology and Circuits held in June, the two approaches — V-Die from a Korean research collaboration and MOSAIC from a University of Tokyo-led group — both explore the same broad idea of standing DRAM memory dies on their edges instead of stacking the memory dies only upward like conventional HBM.

The Korean proposal, called Vertical-Die (V-Die), was presented by researchers at the Ulsan National Institute of Science and Technology (UNIST). The design rotates custom DRAM dies upright, drops through-silicon vias to free die area for more memory cells, gives each die its own bottom-edge I/O, and runs liquid-cooling channels between adjacent dies. In simulations against an HBM4 system at equal capacity, the V-Die system reportedly achieved 540 tokens per second on a GPT-3-sized workload, compared to 296 tokens per second for HBM4.

The Japanese project, MOSAIC, takes a similar “sideways stack” idea but focuses on the practical difficulty of connecting so many vertical dies to a GPU or package substrate. Presented by University of Tokyo researchers, the MOSAIC work uses orthogonal die stacking and a contactless die-to-die interface, in which data is transferred through tiny inductive coils rather than requiring every signal pad to land perfectly on a physical contact. The researchers say the prototype interface achieved up to 4 Gbps per channel, while the memory structure could double HBM4-class capacity in a DRAM-on-GPU configuration.

Both projects aim to solve the growing problem of AI chips being held back by memory. Modern accelerators can perform enormous amounts of computation, but large, powerful models depend on moving huge amounts of data between memory and compute. This is why HBM has become one of the defining technologies of modern AI hardware.

The technology addresses the memory wall by stacking multiple DRAM dies vertically on a base die and placing that stack very close to the processor. Nvidia's Blackwell Ultra B300, for instance, carries up to 288GB of HBM3E memory, without which much of the silicon would sit idle waiting for data. The dies are connected via through-silicon vias (TSVs) — tiny vertical channels etched through the silicon and filled with metal.

The stack then communicates with the GPU over an extremely wide interface, often routed through a silicon interposer or an advanced package. This is the core reason HBM can deliver terabytes per second of bandwidth: it uses a very wide, very short data path instead of sending memory traffic across a motherboard, as with conventional DIMMs (Dual In-line Memory Modules), physical sticks of RAM used in computers.

However, that same structure creates several problems. While taller stacks add more capacity, they also make it harder to remove heat. Heat generated in the lower dies and at the high-speed interface must pass through layers of silicon, bonding materials, underfill, and package structures before it reaches a heat spreader. Furthermore, TSVs consume die area that could otherwise be used for memory cells, and as bandwidth rises, more routing and I/O place additional pressure on both signal integrity and packaging costs.

HBM4, the latest generation of HBM, addresses a number of these challenges. Meanwhile, companies such as SK hynix, Samsung, and Micron are racing to improve speed, capacity, base-die performance, and thermal management. SK hynix has already shown iHBM, which embeds cooling elements into the HBM interface area, and Samsung has shown an HBM5 mockup with Heat Path Block cooling to more directly extract heat from the stack. However, they all retain the same upward stacking structure.

This convention is what V-Die and MOSAIC are challenging. By standing DRAM dies upright, the researchers expose far more silicon surface area to the cooling path. In theory, this turns the memory stack into something closer to a heat-sink fin array, where heat can move laterally and escape more directly instead of being trapped in the middle of a thick vertical pile. It also opens the door to new connection schemes along the bottom or side of each die, rather than forcing every die to communicate through TSVs running vertically through the stack.

For V-Die, the key shift is removing TSVs from the memory dies and replacing them with bottom-edge connections. Each DRAM die gets its own I/O along the bottom edge and connects directly to the substrate, with links reportedly spaced every 20 microns. The team says this layout gives four times as many connections as HBM4 and cuts memory read time by 37%, although some signals must travel farther across the package to reach the processor.

Cooling is the other half of the V-Die argument. The proposal places microfluidic cooling channels between adjacent upright DRAM dies, allowing coolant to dissipate heat closer to its source. According to the researchers, this could keep the stack around 45°C, far below the 80°C-plus range associated with dense HBM systems. In a simulated 16-die stack matched to H100-class hardware on a GPT-3-scale model, V-Die hit 540 tokens per second, compared to HBM4's 296, and cut first-token latency by 32%, or about 24 milliseconds.

MOSAIC, meanwhile, is focused on making the sideways stack manufacturable. Because the dies are assembled flat and then turned on edge, even a few microns of die-thickness variation across dozens of dies can add up to an alignment miss where the signal pads no longer land. The Japanese team’s answer is a contactless interface based on inductive coupling. One side of the memory die carries oblong coils, while a corresponding set of coils sits on the substrate or mating chip. Current in one coil induces a signal in the other, allowing data to cross the small gap without a direct metal-to-metal signal contact. This eliminates the need for precise overlapping, giving the package greater tolerance for assembly variation. Power, which requires fewer, larger connections than data, can still be supplied via physical contacts on the sides of the memory cube.

The VLSI MOSAIC prototype achieved up to 4 Gbps per channel and demonstrated TSV-free 3D integration for a memory-on-GPU layout. The team says the approach can enable twice the memory capacity of HBM4 without significantly increasing peak temperature. A related bump-MOSAIC hardware demonstration at ECTC used 100-micron-pitch microbumps, achieved stacking alignment within 6 microns as verified by X-ray CT, and showed a configuration with three times the thermal conductivity of conventional stacking while adding up to 30% more memory capacity.

While the results look promising, neither V-Die nor MOSAIC is close to replacing commercial HBM. Neither is close to shipping. V-Die is still a proposed architecture, with a prototype in the works to validate its thermal and electrical behavior; MOSAIC has proof-of-principle hardware, but the researchers have yet to show it scales to commercial DRAM capacity, yield, cost, and reliability.

Still, any viable solution to the multifaceted AI memory problem is a welcome development. SoftBank and Intel’s Z-Angle Memory (ZAM) and NEO Semiconductor’s 3D X-DRAM — both still in development — aim to solve the constraints of conventional memory. Meanwhile, the overall market is already feeling the squeeze on price and availability, even as memory makers divert capacity toward the more lucrative AI HBM and server products, driving consumer RAM prices even higher.

Micron has said it will invest up to $3 billion in the U.S. semiconductor supply chain, with $500 million of that going to GlobalWafers as strategic financing for its 300 mm raw silicon wafer plant in Sherman, Texas, alongside a 10-year agreement giving Micron access to that plant's wafer output. In a separate announcement, the memory maker raised its planned U.S. spending to more than $250 billion through 2035, up from $200 billion, and confirmed the first concrete pour at its Clay, New York campus more than a quarter ahead of schedule.

Sherman is the sole operating facility in the U.S. capable of producing advanced 300 mm raw silicon wafers, the substrate on which every leading-edge DRAM, NAND, and logic die is built. GlobalWafers opened the plant in May last year and holds a $406 million CHIPS Act award covering the site and a silicon-on-insulator facility in St. Peters, Missouri. The 142-acre campus is designed for up to six phases, one of which is running. Micron's other American sites draw their wafers from Japan, Taiwan, Germany, and South Korea; Shin-Etsu, SUMCO, GlobalWafers, Siltronic, and SK Siltron together control the overwhelming majority of global 300 mm supply, making raw silicon the most concentrated layer in the chip space.

Doris Hsu, chairperson and CEO of GlobalWafers, set out her terms for building phase two at Sherman during the plant's opening last year, telling Reuters the company needed profitability at the first two phases, customers willing to sign long-term contracts, reasonable pricing, prepayments, and government support. Thursday's announcement supplies most of that list in a single transaction.

Wafer suppliers spent the 2023-2024 downcycle protecting margins rather than adding capacity, and SUMCO is winding down 200mm production at Miyazaki this year while holding the line on new 300mm expansion. Customers, not suppliers, are therefore now underwriting the capacity. The last time the industry did this, during the 2017-2018 megacycle, chipmakers signed prepaid long-term agreements that turned into liabilities when pricing rolled over.

Silicon wafer shipments reached 3,275 million square inches in Q1 2026, up 13.1% year over year, with SEMI.org attributing the growth to AI data center demand across advanced logic, memory, and power devices. Micron's first new Idaho fab, ID1, is expected to begin wafer output in mid-2027, and production at Clay isn't expected until around 2030. The company began making 1-alpha DRAM at its Manassas, Virginia fab in May.

Micron told investors last December that it can serve only half to two-thirds of customer demand, and nothing announced Thursday changes the supply position of DRAM this year or next.

Rapidus is bidding Japan's entire return to leading-edge logic on one fab in Chitose, Hokkaido, and the schedule now turns on a 2027 mass-production target for a 2nm process that no high-volume customer has yet committed to.

Since opening the IIM-1 pilot line in April last year, the company has run wafers through Japan's first mass-production-grade EUV scanner, produced a 2nm gate-all-around prototype that reached its expected electrical characteristics in July, and closed a ¥267.6 billion funding round in February that made the Japanese government its largest shareholder. CEO Atsuyoshi Koike said the same month that more than 60 companies are in talks over 2nm capacity, but not one has yet signed a volume agreement. Given that its entire production base is the single IIM-1 facility, this leaves Rapidus with no diversification and no fallback site if the node doesn’t go ahead as planned.

However, the fab has the hopes of an entire nation pinned on it, and its plans are promising. Here's the breakdown.

A ticking clock on IIM-1

IIM-1, short for Innovative Integration for Manufacturing, broke ground in September 2023 at Bibi in Chitose, with the cleanroom completed in 2024. ASML delivered a TWINSCAN NXE:3800E in December 2024, the first mass-production-grade EUV system installed in Japan, and the tool completed its first exposure on April 1st last year. The pilot line also began operating that month.

Rapidus is currently targeting 2027 for mass production, but the company has given that date without any further qualification, with its business plan simply pointing to production beginning in the second half of fiscal 2027 and scaling to full volume in 2028. The same plan sets out a capacity ramp from roughly 6,000 wafer starts per month at the outset to around 25,000 within the first year, a fourfold increase that Rapidus is counting on to bring per-wafer costs down.

IIM-1’s siting in Chitose offers the abundant water that wafer cleaning demands, a cool climate that eases cooling loads, and some of Japan's strongest renewable-energy potential across wind, solar, and hydro. Local and prefectural authorities have organized around the project under a “Hokkaido Valley” initiative that aims to build a semiconductor cluster spanning Tomakomai, Chitose, and Ishikari.

The 2nm process

Rapidus’s 2nm node is a gate-all-around nanosheet design derived from the IBM 2nm process announced in 2021, the product of a partnership signed in December 2022. Rapidus engineers worked alongside IBM at the Albany NanoTech Complex in New York to learn the node before transferring it to Chitose. More than 150 Rapidus engineers were dispatched to Albany across 2023 and 2024 to learn the node, with roughly 80 later returning to Chitose to transfer and tune the process for production, according to IBM.

The differentiator the company is leaning on is manufacturing flow, with IIM-1 running single-wafer front-end processing throughout, branded as Rapid and Unified Manufacturing Service, with per-wafer data fed into AI models that Rapidus says will accelerate yield learning and shorten turnaround compared with the batch processing used by TSMC and Samsung. It’s understood that the 2nm Process Design Kit (PDK) reached early customers in Q1 this year. Still, Rapidus hasn’t yet published a yield figure, and its public claims extend only to the prototype attaining expected electrical characteristics.

The program extends beyond the wafer, with Japan’s New Energy and Industrial Technology Development Organization (NEDO) approved fiscal 2026 budget for Rapidus providing funds for chiplet and package design and manufacturing technology for 2nm-generation semiconductors, alongside front-end work. The company has also floated panel-level glass-substrate packaging as part of its longer-term roadmap. Building that back-end capability in Chitose rather than outsourcing it would mirror the integrated approach Intel and Samsung take.

Japan’s government as a shareholder

Rapidus’s February funding round closed at ¥267.6 billion, or about $1.7 billion, split between ¥100 billion from the government through the Information-technology Promotion Agency and ¥167.6 billion from 32 private companies. The state investment, the first made possible by a 2025 revision to Japan's subsidy law permitting government equity in Rapidus, made Tokyo the largest single shareholder, with a golden share giving it veto power over major decisions, including share transfers and technology partnerships.

That round sits on top of a much larger commitment from November, when Japan's Ministry of Trade and Industry added approximately ¥1 trillion in support across fiscal 2026 and 2027, lifting total planned government backing to about ¥2.9 trillion. The government added a further ¥150 billion in equity in early June, taking Rapidus’s combined capital and capital reserves to around ¥425 billion. The shares the state holds are structured as largely non-voting, keeping its formal voting position near 11.5%, but they convert to a controlling stake of roughly 60% if performance deteriorates, a clause that pairs with the golden share to give Tokyo both upside alignment and a downside lever.

Rapidus’s buildings and equipment are also currently owned by Japan's New Energy and Industrial Technology Development Organization (NEDO) and leased back, with the company previously obligated to buy them by fiscal 2027. The government now plans to construct fab buildings and tools with public money across fiscal 2027 and 2028 and transfer them to Rapidus as in-kind contributions in exchange for shares, removing that purchase obligation and converting what had been grant funding into direct ownership.

The customer conundrum

Koike said in February that Rapidus was in discussions with more than 60 companies and had issued preliminary price quotations to around 10 of them. The names attached to those talks in reporting by TrendForce are IBM and the Canadian RISC-V accelerator startup Tenstorrent, with Fujitsu, a founding investor, separately weighing whether to outsource a 1.4nm CPU for a successor to its Fugaku supercomputer around 2029.

The design partnerships Rapidus has actually signed, however, are with smaller players building energy-efficient AI silicon. Tenstorrent, the firm led by chip architect Jim Keller and currently being considered for takeover by Qualcomm, agreed back in 2023 to co-develop an edge-AI accelerator on the 2nm node under a NEDO and Leading-edge Semiconductor Technology Center (LSTC) project, with Tenstorrent handling the CPU and Rapidus' AI Chip Design Center building the accelerator. Rapidus signed a separate memorandum of cooperation with RISC-V inference designer Esperanto Technologies in May 2024.

Neither of these amounts to the committed high-volume order that Rapidus needs, and fast. Koike has described interest as growing “like a runaway steam engine,” but interest is not the same as allocation. Rapidus’s cost model depends on filling the 25,000-wafer ramp, and a fab running well below capacity carries the same fixed depreciation as a full one. The company has said its homegrown 2nm chips could cost around 10 times more than Japan’s current mainstream parts, a premium that’ll only narrow with volume.

Japan's two-track strategy

Rapidus is the leading half of a national plan that’s running on two tracks. The other is TSMC's JASM venture in Kumamoto, on the southern island of Kyushu, where a first fab backed by Sony, Denso, and Toyota began mass production in December 2024 on mature 12nm, 16nm, 22nm, and 28nm nodes aimed at automotive and industrial chips.

A second Kumamoto fab broke ground in 2025, and its planned node was upgraded twice, first to 4nm and then to 3nm, with production targeted around 2028. Tokyo is therefore funding mature and specialty capacity through a proven foreign operator in the south while betting on a domestic startup to reach the leading edge in the north. The Kumamoto plants carry far less technical risk and are already shipping; Rapidus carries nearly all of the program's execution risk and none of its proven output.

Even as the 2nm line ramps, Rapidus plans to begin 1.4nm process development in 2026, start construction on a 1.4nm fab in 2027, and reach mass production around 2029. The node leans on the company's research ties: Rapidus joined imec's core partner program in April 2023, giving it access to the Belgian institute's pilot line, and imec's position is that 1.4nm single-patterned layers require High-NA EUV, the 0.55 numerical-aperture tool that resolves the most critical metal layers in one exposure rather than several. Total lifetime investment is expected to exceed ¥7 trillion, with roughly ¥5 trillion needed just to reach stable 2nm production, according to figures cited by both TrendForce and Nikkei.

Rapidus’ financials highlight how far all this is from being self-sustainable, having posted a ¥375 million loss for fiscal 2025 with total assets of ¥749.5 billion, while still aiming to raise around ¥1 trillion from private investors. The ASEAN+3 Macroeconomic Research Office has been cited as estimating that committed funding still falls short of the roughly ¥5 trillion needed for stable production, dependent on a private investor base that has yet to materialize at scale.

Meanwhile, TSMC moved its N2 node to volume production in late 2025, and Samsung began first-generation SF2 mass production the same year, which puts Rapidus roughly two years behind both on a node that customers can already buy elsewhere with proven yields. There’s also something of an adversarial backdrop developing: TSMC employees were reportedly accused last year of taking 2nm trade secrets said to be destined for Rapidus, an allegation a Japanese government official later characterized as non-critical. The episode has no confirmed bearing on Rapidus’s process, which is built on IBM IP.

Rapidus is targeting operating profitability around fiscal 2030 and an IPO in fiscal 2031, a timeline that assumes the 2027 ramp lands on schedule and that the customers now in talks convert into committed volume. Three milestones will indicate whether those targets are possible: a named customer with a committed volume order, evidence that 2nm yields are tracking toward the levels TSMC and Samsung already run at, and confirmation that the capacity ramp is hitting its 25,000-wafer target.