A new GitHub repository dubbed ram-altman features a script to monitor your PC’s RAM usage and report back to the eponymous OpenAI boss. Sam Altman infamously described people having spare, underutilized DRAM in computers at home as “quite terrible” in a recent podcast. Thus, developer Iain Kay was inspired to write a bash script that emails the OpenAI boss once a day to report on any RAM that is underutilized. Clearly this is not a serious tool, or rather “The memory accounting is. The correspondence isn't,” says Kay.

ram-altman leans on the MemAvailable query, which returns the kernel's own estimate of how much memory programs can claim without swapping, explains the developer of this script. When installed, it checks every five minutes and emails Altman once a day if you are found to be wasting this precious resource.

The emails take the .CSV file logs of your RAM use throughout the day as the data source to compose a summary email. These script-generated messages rotate through eight subject lines, 10 humorous message boilerplates, and six signoffs. Sample emails can be seen on the ram-altman.lol website. Altman’s email address isn’t supplied as part of the script.

If your machine is using 90% or more of its RAM, then you won’t be reported to the OpenAI boss for wasting memory. Also, if you don’t want to disturb Altman, you can run the tests without emailing anyone with the terminal command: bash ram-altman.sh --dry-run

The developer isn’t too scathing of the OpenAI boss. Kay quotes Altman’s explanations that his remarks were taken out of context. Moreover, the dev doffs his cap to the artificial intelligence leader’s humorous display name change to ‘Ram Altman’ on X last week. That’s where the name for this script came from.

ram-altman is a free bash script available on GitHub. It runs natively on Linux. On Windows, you can use WSL to run it, but someone has ported it for PowerShell too. It won’t run on Mac, but Altman and his minions would find it inconvenient, at best, to remove your soldered-down Apple RAM.

The latest CPU-Z hardware survey data shows 32GB and 64GB memory configurations down 2.5% and 18% year on year, respectively. The driving factor is no mystery: High-capacity memory has become a luxury in modern PC builds. The AI rush is still gobbling up the global DRAM supply, so prices for the best RAM options across DDR4 and DDR5 have gone through the roof.

If you are not familiar with CPU-Z, it is a free program that gives you a detailed breakdown of the hardware inside your system. It only tracks systems where it is actually installed and running, so it does not report monthly retail sales figures. Do not take the data as sales figures in any sense. They represent CPU-Z's active user base.

32GB and 16GB are common configurations that have grown over the years. According to the gathered data, 32GB configurations lead CPU-Z's user base with a 37.2% share, with 16GB configurations close behind at 33%. Not a surprise, really, since applications and games have grown more memory-intensive. 16GB has been the baseline for a long time now, and 32GB is now the sweet spot for many people, even gamers.

On the flip side, 8GB configurations have been steadily declining. They make up only 11% of the surveyed systems. 8GB systems are rare nowadays. You may still find them in legacy systems, basic office machines, or extremely budget-limited builds where performance takes a backseat. Meanwhile, higher-end configurations, including 64GB and 24GB, are still in the minority at 7.3% and 2.3%, respectively.

For the first time, the CPU-Z developer recorded a noticeable decline in higher-capacity configurations. Specifically, 32GB configurations fell 2.5% year over year, while 64GB options dropped a significant 18%. This is likely due to the steep rise in memory prices, which has forced consumers to reconsider the cost-benefit of larger capacities.

As the price per gigabyte goes up, buyers are opting for more affordable capacities. Lower-capacity memory kits have seen a somewhat revival. The 16GB configuration, often considered the minimum, has rebounded by 12.9%. Similarly, 8GB configurations, which were previously in sharp decline, grew 5.5%.

Interestingly, 24GB configurations also increased by 19.7% and have become a compromise for consumers who need more than 16GB of memory but do not want to spend a lot of money on a premium 32GB memory kit.

How much money are you willing to spend during the Black Friday sales?

The current distribution between DDR4 and DDR5 memory types reveals that DDR4 remains the dominant memory standard at 54.5%. In contrast, DDR5, despite being the latest memory technology, is still in its early adoption phase at 32.9%. DDR4 has been the de facto standard for almost a decade now, so it will take time for DDR5 to overtake it.

Nonetheless, the noticeable 6% growth in DDR4 and 2.9% decline in DDR5 suggests budget-conscious consumers are sticking with platforms that still embrace DDR4, such as AMD's Zen 3-powered Ryzen 5000 (codenamed Vermeer) or Intel's 13th Generation Raptor Lake processors. CPU-Z's processor charts show a significant increase in Zen 3 chips, including the Ryzen 7 5700X, Ryzen 5 5600, and Ryzen 5 5500, with figures up to 42.8%, 36.1%, and 67.3%, respectively.

Although both DDR4 and DDR5 have increased in price, the former remains slightly more affordable. Companies are supporting the effort too, such as AMD rereleasing the Ryzen 7 5800X3D, vendors restarting DDR4 and DDR4 motherboard production, or Intel preparing rewarmed Raptor Lake Next chips for 2027.

A recent report from The Information suggested that TSMC is exploring 3D DRAM production at Nvidia's request as surging demand for AI hardware strains global DRAM supplies and drives up prices. If the proposal were to come to fruition, it could mean a new, albeit prone to cyclical risks, business for TSMC and could dramatically expand its role in the AI supply chain. For its part, TSMC states that it is a pure-play logic foundry and plans to remain a logic foundry, which essentially means a denial of the report.

"Please note that TSMC focuses on our core business at all times, which is dedicated IC foundry," a TSMC spokesperson told Tom's Hardware. "Our mission is to be the trusted technology and capacity provider of the global logic IC industry for years to come."

Despite the denial, according to two people familiar with the initiative cited by The Information, TSMC has begun preparing plans for 3D DRAM manufacturing following a request from Nvidia, its largest customer. The initiative is reportedly overseen by Hsu Kuo-chin, TSMC’s vice president responsible for advanced packaging and former head of Micron’s Taiwanese operations. The effort comes amid widespread memory shortages that turned memory from a commodity into a strategic asset that could determine whether a company can ship its products to customers or not.

Although TSMC works closely with DRAM producers as it packages memory into system-in-packages (SiPs) for its customers, the company lacks the expertise and production capacity to make DRAM, let alone 3D DRAM. Meanwhile, given that 3D DRAM is years away even for major memory makers, pursuing a 3D DRAM strategy cannot solve memory shortages for at least five years.

Unlike conventional DRAM, which arranges memory cells in a single plane, 3D DRAM places multiple levels of memory cells vertically to increase capacity per wafer. All three leading DRAM makers — Micron, Samsung, and SK hynix — are working on their 3D DRAM projects. However, Micron's DRAM strategy includes at least four more planar DRAM process technologies before 3D DRAM becomes a reality.

While TSMC has arguably the industry's best logic process technologies, DRAM production requires entirely different manufacturing processes, which TSMC would have to develop, should it pursue making memory for its customers. Meanwhile, producing 3D DRAM requires completely different fabrication techniques to construct multiple memory-cell layers while controlling defects and maintaining acceptable yields. It is hardly possible to develop a 3D DRAM manufacturing process without having a competitive planar DRAM process technology, and TSMC does not have one.

One of the options for TSMC to enter the DRAM business would be to acquire a small specialty memory producer that has its own fabrication capability. This would give TSMC a credible route into advanced DRAM manufacturing without having to develop the underlying memory technology and IPs from scratch. However, small makers do not have leading-edge commodity DRAM nodes, so TSMC would still need to invest billions of dollars and years of R&D into development of a leading-edge process technology for DRAM.

However, entering DRAM manufacturing would expose TSMC to substantial market risks. Memory shortages frequently encourage capacity expansions that eventually create oversupply, depressing prices and profitability. Such uncertainty could surely make TSMC think twice before going down the DRAM route. Furthermore, entering the DRAM business could also complicate TSMC's relationship with large DRAM makers in general, and SK Hynix, which partnered with the foundry in 2024 to manufacture logic base dies for next-generation HBM products, in particular.

TSMC’s potential entry into DRAM manufacturing could also raise antitrust questions, particularly if the company combines its dominant position in leading-edge logic manufacturing, leading position in advanced chip packaging, and ramping memory production. Regulators could examine whether such vertical integration would enable TSMC to favor its own memory products or disadvantage competitors that lack such a vertical integration. Then again, in-house DRAM development by TSMC could also strengthen competition by introducing another supplier into a market dominated by just three manufacturers.

Yet, TSMC does not necessarily need to manufacture DRAM to capitalize on growing demand for advanced memory. Instead, it could capture a larger share of the value generated by DRAM by producing sophisticated logic base dies for HBM, integrating memory with processors using its SoIC hybrid bonding technology, and developing customized memory solutions with partners such as GUC and established DRAM manufacturers. This approach would allow TSMC to expand its presence in the advanced memory market without investing billions of dollars in developing competitive DRAM process technologies from scratch and/or building additional fabs for tens of billions of dollars.

Team Group CEO Chen Ching-wen said during the company’s November 2 earnings call that the memory chip shortage is expected to become worse from the end of 2026 until the end of 2027. BigGo Finance quoted Chen as saying that there is “no downward price trend whatsoever,” and that some purchasers could face a scenario “even money can’t buy goods.” He also noted that the spread between spot and contract prices for memory chips ranges from 30% to 50%, meaning short-term supply is significantly more expensive than long-term contracts.

"We have contracts but can't get enough volume, so we have to go to the spot market and pay a premium to grab supply," the Team Group chief said during the briefing. Contract prices for 16GB DDR5 chips climbed from $8.70 in October 2025 to $48 by September 2026. This is an increase of more than 550% in the past 12 months, and it seems that the price hikes are not letting up. He also estimated that supply and demand will not balance until the latter half of 2028 or perhaps even later. “How can prices fall when there’s nothing left?” said the CEO.

The Chairman also noted that even though CXMT and YMTC have increased their market share to almost 10%, most high-end DRAM and NAND flash chips still come from Kioxia, Micron, Samsung, and SK hynix. Even then, the prices for the chips that these Chinese companies make still track the market closely, meaning they’re not the budget savior that many were expecting. As such, he expects that pricing for budget components will not ease until 2029, while high-end chips will continue to remain in short supply.

These estimates go against Acer CEO Jason Chen’s prediction that component pricing will reverse by the latter half of 2027. Chen suggests that only high-end chips, like LPDDR5X-9600 and Nvidia N1-series SoCs, will remain in shortage while mainstream parts will finally go down. PCs will still experience hikes between 5% and 20% until the end of this year, plateau during the first half of 2027, before finally going down. Chen claims that most major suppliers want to hype the shortage for as long as possible to preserve their margins.

Unfortunately, there’s no way for us to know which of these predictions will come true. While consumers would gladly want to have a break from the nearly continuous price hikes that PC parts and components have been experiencing over the past months, the AI data center build-out is apparently continuing, even as many Americans voted against it.

Last month, Micron disclosed its DRAM and NAND memory roadmaps for the next several years, revealing plans to use wafer bonding, new materials that enable making NAND cells smaller, High-NA EUV lithography, and detailing its moves toward 3D DRAM. Perhaps the most revealing part of Micron's story is that the company plans to expand its portfolio of custom DRAM and NAND products as AI developers increasingly require memory and storage solutions optimized for their unique processor architectures and specific workloads.

" DRAM is nearing atomic limits at this point: although we have confidence in several more planar nodes, we are very focused on making sure that we introduce 3D DRAM at the optimal time from a cost and performance point of view," said Scott DeBoer, president and chief technology and products officer at Micron, at the company's event earlier this month. "[With 3D NAND, we are] really focused on new materials densifying the cell architecture, and continuing to focus on that XYZ scaling going forward."

DRAM: 4F2 cells axed, High-NA EUV lithography, new materials, and 3D DRAM enable future scaling

In a surprising move, Micron decided to abandon plans to produce DRAM with 4F² memory cells, unlike its rivals at CXMT, Samsung, and SK hynix, citing the lack of a viable scaling path beyond where Micron is today. Instead, Micron's roadmap for the coming years includes wafer bonding, High-NA EUV lithography, new materials, and eventually 3D DRAM. The company plans to begin mass production of its next-generation 1δ memory in the second half of 2027, while subsequent 1ε, ζÅ, and ηÅ technologies are at various stages of development. In parallel, Micron is developing two generations of 3D DRAM that could eventually succeed conventional planar memory.

Micron's current 1γ (1-gamma) DRAM process technology, which is in high-volume manufacturing (HVM), is the company's first DRAM node to use EUV lithography. Previously, Micron had used multipatterning with DUV lithography and remained competitive with Samsung and SK hynix, which relied on EUV for critical layers.

Micron's next-generation 1δ (1-delta) fabrication process is currently in the yield ramp stage and is scheduled to enter mass production in the second half of 2027. The company expects the technology to increase bit density by mid-20% compared to 1γ, while advanced high-k metal gate (HKMG) CMOS, new materials, angstrom-level process control, and equipment intelligence should improve performance, power efficiency, and ultimately yields as well as costs.

Micron plans to manufacture 1δ DRAM in the U.S. and use the technology for next-generation DDR, LPDDR, graphics memory, HBM5, vertical HBM (vHBM), and vertical Edge Inference Memory (vEIM) products. Meanwhile, to make HBM5, vHBM5, and vEIM products, the node will also support additional features like through-silicon vias (TSVs) and other elements to improve thermal performance.

The subsequent 1ε (1-epsilon) process will rely on wafer bonding, which will enable Micron to produce different structures on separate wafers and then bond them together. This approach could increase flexibility in memory design and manufacturing, but Micron has yet to disclose its plans to implement wafer bonding, which structures it will bond, or what improvements in density, performance, and power consumption the technology will provide. The process is currently under development, and there is no announced production schedule.

Micron's ζÅ (zeta-angstrom) production node is currently in early development and will introduce High-NA EUV lithography to memory manufacturing, which will enable further reductions in critical dimensions. The company has not disclosed how many layers will require High-NA lithography, the expected density improvements, or when the technology will enter mass production. However, it is obvious that the node will not be here until at least 2030, years after Samsung and SK hynix adopt High-NA EUV at their DRAM fabs (planned for 2028).

The ηÅ (eta-angstrom) process represents the most distant generation on Micron’s disclosed planar DRAM roadmap and is currently in the pathfinding stage. After Micron inserts High-NA EUV lithography into its DRAM production flow, the company intends to bet on other methods of scaling. Although Micron mentions new materials, it hasn't identified them or explained how they will affect device structures. These could include new photoresists, deposition precursors, dielectric materials, or conductive materials that would enable the company to manufacture smaller transistors and capacitors, and ultimately increase DRAM cell density.

In any case, Micron's roadmap is focused on continuing development of DRAM based on 6F² cells, which differs from the plans of CXMT, Samsung, and SK hynix.

3D1 and 3D2: Transition to 3D DRAM is looming

In parallel with conventional DRAM development, Micron is working on two generations of 3D DRAM, currently called 3D1 and 3D2. Unlike planar DRAM, which primarily relies on smaller memory cells to increase bit density, 3D DRAM would use the vertical dimension to accommodate more memory cells within a given area. Micron intends to introduce the technology when it becomes competitive with conventional DRAM in terms of manufacturing costs and performance. The company has not disclosed architectures, layer counts, or density targets.

In fact, while Micron has outlined its future memory architectures through 2030, its DRAM manufacturing roadmap provides a firm production window only for the 1δ process, which is scheduled to enter high-volume manufacturing in the second half of 2027. The company has not disclosed production dates for subsequent planar DRAM nodes or either generation of 3D DRAM.

Custom HBM and vertical memory architectures

In addition to conventional DRAM, Micron plans to use its future manufacturing technologies for HBM4E, HBM5, HBM5E, and new vertically integrated memory architectures. Starting with HBM4E, the company will offer both standard and custom HBM products, which will be followed by custom HBM5E, vHBM, and vEIM (vertical Edge Inference Memory). All of these will mark the re-emergence of custom memory in mass-produced products.

Custom HBM4E (cHBM4E) will enable Micron's customers to shrink memory I/O width and/or integrate additional logic into the memory's base die to free up valuable die space for compute and optimize performance and power consumption for specific AI accelerators. According to Scott DeBoer, Micron’s president and chief technology and products officer, some of these functions would otherwise reside in the ASIC itself, so moving them closer to memory should improve overall system efficiency.

"When we co-design a base die, and the certain logic elements that are desired to be put in that base die are generally an offload from GPU circuitry anyway onto the base die to put it closer to the memory," said DeBoer. "Moving what makes more sense onto the base die will still be a reality in [the] vertical HBM timeframe as well."

To support these capabilities, Micron intends to use advanced foundry process technologies for the base dies of both standard and custom HBM products, although it has not disclosed specific nodes. For custom designs, the company will select the most cost-effective process that meets customer requirements. For example, Micron expects HBM4E to require more advanced CMOS technologies to meet its performance and power targets.

Further down the road, Micron intends to introduce vertical HBM (vHBM), which will stack memory directly on top of ASICs and CPUs rather than next to them on an interposer. This architecture promises substantially higher bandwidth, thanks to dense vertical connections (as well as significantly lower latencies) thanks to adjacent placement, but it is also set to create considerable challenges related to power delivery and heat dissipation. To address them, Micron plans to use hybrid bonding for advanced interconnects, integrated heat spreaders, and thermally aware designs. Interestingly, the company expects conventional HBM and vHBM to coexist in some designs, where vHBM provides maximum bandwidth, while traditional HBM serves capacity requirements.

Another technology under development is vertical Edge Inference Memory (vEIM), which shares many of its packaging and integration technologies with HBM, but targets applications that require power efficiency more than maximum bandwidth. Micron's 1^st Generation vEIM aims to deliver formidable HBM4-like 2 TB/s of bandwidth while consuming less than 1 picojoule per bit of data transfer energy.

Both architectures will require close cooperation with customers to optimize memory, logic, packaging, and thermal characteristics for particular applications, so Micron will need to work with its clients to make vHBM and vEIM successful. Interestingly, Micron's customer-specific development efforts extend beyond HBM and EIM.

For example, the company is collaborating with Meta to optimize LPDDR6 for data center applications, which primarily include reliability, serviceability, and availability. Micron expects LPDDR6 to reduce power consumption by approximately 35% compared to LPDDR5, which will be very important for dense memory deployments. The company also intends to develop DDR6 — which targets 2X DDR5 bandwidth — in cooperation with major customers to better understand and ultimately meet their needs.

Speaking of customer cooperation, DeBoer stresses that Micron now collaborates with customers from the earliest stages of product definition through joint design, development, validation, and volume production. According to the executive, this approach differs substantially from how the company worked with customers previously.

"Across our AI co-invention opportunities we are co-imagining, co-designing, co-developing, co-validating, and then delivering at scale," DeBoer said. "This opportunity is truly unique. It is very different than the way we interacted with customers even three or four years ago."

Advanced CMOS: More than 10X performance improvement

In addition to shrinking DRAM cells and developing vertical memory architectures, Micron is developing advanced CMOS technologies for peripheral circuitry. The company's roadmap includes several generations of DRAM CMOS logic with high-k metal gate transistors, followed by 1^st and 2^nd Generation 3D CMOS technologies.

Micron expects these advances to increase its CMOS logic performance by more than 10X between 2020 and 2030, which should help the company address the growing bandwidth and power requirements of AI-oriented memory products.

3D NAND: From next-gen 400L 3D NAND to AI-oriented NAND

Although Micron's event was mostly dedicated to the future of DRAM, the company also shared some details about its upcoming NAND innovations, which include 11^th Generation 3D NAND with 400 layers, post-G11 3D NAND, and AI-oriented NAND memory that either offers high bandwidth or high IOPS.

Micron's next-generation G11 (N170) 3D NAND technology represents a substantial departure from its current G9 (N160) process. The company plans to increase the number of active memory layers from 276 to more than 400, introduce wafer-on-wafer bonding, and implement an industry-leading memory cell pitch.

These improvements are expected to double the bit density of G11 3D NAND compared with G9 3D NAND, presumably from 21 Gb/mm² to 42 Gb/mm² in the case of 3D TLC devices, which should substantially reduce manufacturing costs per bit once the technology reaches mature yields.

In addition to increased storage density, G11 also targets a 50% increase in I/O speed compared with G9, which implies a potential transfer rate of approximately 5,400 MT/s. Furthermore, Micron expects to reduce data transfer energy consumption by more than 25% per bit, an important improvement for high-capacity SSDs and AI storage systems that tend to move huge amounts of data.

One of the most important changes with G11 is the adoption of wafer-on-wafer bonding, which lets Micron manufacture memory arrays and the periphery and I/O circuits on another wafer, then bond them together. Chinese manufacturer YMTC has used this method to maximize storage capacity and performance, so it is not surprising that Micron and other memory manufacturers are adopting the technique as well.

Micron expects to start mass production of G11 3D NAND in the second half of 2027.

Improving 3D NAND past G11: New materials and further XYZ scaling

Micron intends to continue improving 3D NAND beyond 11^th Generation through a combination of new materials, denser memory cell architectures, and more energy-efficient devices and data paths. Specifically, Micron is investigating high-mobility materials that could improve the electrical characteristics of future memory devices, as well as ultra-dense cell architectures intended to increase storage density beyond what an increase in active layers provides.

Meanwhile, more energy-efficient circuitry and data paths should help offset the growing power consumption associated with higher NAND capacities and faster interfaces.

"Beyond G11, we have a strong roadmap, not going to go into great detail on it today, but really focused on new materials densifying the cell architecture, and continuing to focus on that XYZ scaling going forward," said DeBoer. "[…] The current industry direction and Micron’s direction is scaling both by adding layers [and] also by shrinking the cell dimensions."

The company has not identified the materials it intends to introduce or explained how they will affect memory cell structures. Nor has it provided quantitative density, performance, or power targets for NAND generations beyond G11.

AI-oriented NAND: Higher IOPS and bandwidth

Although Micron is not ready to share details about its G12 or G13 3D NAND generations, the company disclosed that it is developing two specialized NAND architectures for AI applications.

The first — High-IOPS AI NAND — architecture focuses on maximum random I/O performance and uses SLC-based designs with small blocks to accelerate workloads such as vector searches, graph analytics, and AI context management. Micron envisions products capable of delivering approximately 25 million to 100 million IOPS, depending on their configuration, and expects to bring products based on this approach to market over the next couple of years.

The second — High-Bandwidth AI NAND — architecture prioritizes bandwidth over random I/O performance. Micron is investigating vertically stacked NAND devices connected through TSVs and equipped with a logic base die that resides close to AI accelerators, so from many points of view this concept resembles SanDisk's HBF. However, Micron does not believe that simply placing NAND stacks alongside AI accelerators on an interposer offers sufficient advantages. Instead, the company is exploring alternative integration approaches that bring NAND closer to compute resources, but don't necessarily consume valuable shoreline (the perimeter, or edge) of AI accelerators.

"[The High-Bandwidth AI NAND is] more costly and has to be implemented in partnership with customers in a way to ensure that they are meeting the mark and the cost point to drive the value proposition," DeBoer said. "We are enabling TSV-stacked NAND with a logic base die to bring memory closer to accelerators. We do not think placing it along the shoreline of the GPU has merit. Instead, we want to position it closer to the compute itself to take advantage of this high-performance NAND."

These specialized AI-focused NAND architectures will complement Micron's conventional SSD roadmap, which includes plans for drives with capacities of up to 512 TB in the foreseeable future.

Apple is about to feel the squeeze from rising memory prices, with the cost of RAM climbing just as the company heads into its busiest shopping season. According to Reuters, Apple expects to pay more for memory in the December quarter, with the CEO, John Ternus, describing the current price increases as “unprecedented. The company has so far managed to soften the blow by using memory bought at lower prices, cutting costs elsewhere and raising prices on some products. However, it is reported that its manufacturing bill has climbed by $33 billion in just a few months.

But that cushion is getting thinner, and Apple expects memory purchases to become even more expensive into 2027. “What we're seeing with memory pricing right now is unprecedented. And as we said earlier in the September quarter, we did see higher memory costs as compared to the June quarter, which were partly offset by the benefit of carrying inventory and lower costs on certain non-memory components. Now for the December quarter, we expect even higher memory costs, partly offset by a few factors. So as you know, we changed the price on many of our products, including Mac and iPad at the end of June and iPhone in September, and these price increases provided some offset.” Ternus said during Apple’s November 2 earnings call.

Memory is used across Apple's hardware lineup, so sustained price increases could affect manufacturing cost for several product categories—although Apple has not announced another round of price increases. Absorbing higher components could, however, indefinitely become difficult. Dave Nicholson, Chief Research Officer at the Futurum Group, also identified memory prices as a growing pressure point for Apple's margins and hardware pricing through the holiday season and into 2027. According to him, Apple is in a different position from companies pouring hundreds of billions of dollars into AI data center infrastructure. The impact of higher component costs is easier to quantify than the eventual returns on massive AI capital expenditure, he said.

And the warnings from Apple's suppliers suggest that the cost pressure is unlikely to ease quickly. Last month, Samsung, a major supplier of RAM(DRAM), NAND flash storage and OLED displays for Apple, said that memory demand would far exceed supply as AI infrastructure continues to expand. Its memory division also reported a quarter-on-quarter increase in DRAM average prices during the third quarter, while NAND prices rose by high-teen percentages. Senior executive vice president of its memory business warned the supply crunch could extend to 2028 and beyond. Elsewhere, SK Hynix delivered a similar warning, saying it had secured long-term agreements covering more than Half of its production capacity for2027 and 2028. Micron, the third major supplier for Apple aside from Samsung and SK Hynix, is also benefiting from the surging demand for memory. Its latest published outlook warns that supply shortages in memory and storage could take “considerable time” to improve.

We have previously reported several signs of the pressure now confronting Apple. In January, the company was already scrambling to secure memory supplies amid strong demand, with then CEO Tim Cook warning that rising prices could have a greater impact on earnings. By June, rising component expenses had translated into higher retail prices. Apple increased prices across several Mac and iPad models, including a $400 increase to the starting price of the MacBook Pro, due to the RAM crisis. In July, Cook described the memory market as a “hundred-year-flood” and said Apple expected to pay more for memory in the September quarter. The company had also increased its inventory to $11.09 billion as it built a buffer against supply and price pressures.

The latest Steam Survey appears to show that gamers blessed with systems packing 32GB or more RAM and 1TB or more storage are a dwindling breed. This survey is posted without comment by Valve, as usual, but appears to show a significant proportional rise in gamers using 8GB and 16GB RAM PCs, which occurs largely at the expense of the 32GB brigade. The latest stats also show a noticeable increase in storage capacity poverty in the last month. Are the symptoms of the AI industry-induced components crunch now becoming evident among the PC gaming public?

The AI-pocalypse delivered components crunch has been in the headlines for months but it is still jarring to see it impact the vast PC gaming landscape. When we’ve browsed desktop and laptop PCs for the best gaming PC deals over the past months, the trend is clear. Systems that look like they are designed for gamers or enthusiasts are now frequently fitted with just 16GB of RAM as standard, and also feature smaller storage devices that one might have expected. But to see the Steam Survey suggesting that the share of 32GB systems has now collapsed by -5.16% is startling. Only last month, 32GB was the most popular configuration among gamers according to the same survey.

RAM is probably the hardest-hit component segment of AI-driven demand so far. We maintain a RAM price tracking page at Tom’s Hardware and the current state of the market means that DIYers or upgraders need to spend about $250 for 16GB DDR5 or $450 for 32GB DDR5. Those prices change regularly, as well.

Moving onto the sudden recorded change in storage configurations in use by Steam gamers, and we see that folks with 1TB of total fixed storage space or above shrunk by 4.68%. As the categories are currently defined, this appears to show the reduction in the number of systems coming with either a 2TB and 4TB SSD as standard. That’s because the 750GB to 999GB category grew +2.36%, and Windows registers a '1TB' boot disk as a smaller (a quick check shows ours at 924GB). 250GB to 499GB total storage systems were also up a similar amount (+2.30%). Overall, it looks like systems being used for Steam gaming are increasingly fitted with these smaller capacity SSDs. Enthusiasts, gamers, and DIYers wanting to expand their storage at the best prices are advised to keep an eye on our frequently updated SSD price tracking page.

We are currently seeing some extraordinary things in the GPU market, with reports of RTX 5090 and RTX 5080 cards being removed from retail. In the Steam Survey this month the RTX 5080 is still at position 14. However, the joint most popular GPUs are the RTX 5070 and the aging RTX 3060 – both with 3.78% of the market.

We are aware that there are sometimes some strong undercurrents in the Steam Survey that cause unusual fluctuations in the figures. However, the numbers this month don’t look like they have been impacted by a Chinese user or Chinese internet café PC influx, which have previously shown odd trends (such as a rise in Windows 10 usage). Actually, the Steam Survey shows Chinese (Simplified) language users surveyed are sharply down this month, so the survey should more accurately represent the system configurations typical among gamers in the West.

Dave Plummer, former Microsoft engineer and wizard of Task Manager, Windows Pinball, and now TMOG, has an interesting project in his hands once again. After seeing exactly how many zeros were in the price tag for a megabyte of memory for his vintage PDP-11, he decided to take matters into his own hands and conjure up a new RAM board.

The PDP-11 is from 1970, and later models could fit in as much as four megabytes of memory. Plummer enlisted the help of ChatGPT and the EasyEDA online circuit simulator, though he notes that he hadn't done complicated projects like this before. As several PDP-11 models used Q-Bus boards for main system components, he designed this RAM as a standalone card, then tested it on a backplane alongside another board containing the system's M8190 CPU.

Atop it, he placed a Lattice MachXO2 FPGA serving as a memory controller (model 2000HC, if you're wondering), connected to four ISSI 1 MB memory chips. After adding a U2S I/O chip, a bank of DIP switches, comm ports, and sprinkling a handful of capacitors, he had a complete circuit. The M8190 board design has a 22-bit bus and reserves the top 256 KB for I/O and ROM.

However, it wasn't a first-time-lucky project. Plummer encountered a few abortive starts, as he'd never flash-programmed an FPGA chip before. He fixed that after a few attempts, but then he fell into what appears to be a classic PDP-11 trap.

The machine's memory bus design means it can only access entire words (two bytes) at once, and treats the lowest bit in a memory address as a "lane" selector that picks between the low or high byte in the word.

When reading, the CPU will pick out the right byte itself, but Plummer's "memory controller" still needs to return two. Similarly, on writes, the bit selector must be read and then the proper byte selected so that only that will be updated, as the bus lines will still carry an entire word that could otherwise write invalid data.

Plummer seemingly wasn't aware of this before, and one commenter joked that he'd "built 4MB of memory that turned out to be 2MB", to which he replied that the memory "only returns every second word," matching the aforementioned design pattern. Although there are no further updates, since more commenters pointed this out, we assume that he implemented an easy fix in his FPGA code.

One person suggested that he sidestep the entire problem and implement his memory in software via a Raspberry Pi instead, wired directly to the PDP bus. Plummer replied that he'd basically done that already last week with a modern QBone DEC interface board, which in turn contains a Beaglebone Black atop it (similar to a Raspberry Pi).

Having jettisoned 4F² memory cells from its roadmap, Micron must use different methods to continue scaling its DRAM devices in the coming years to keep up with rivals planning to use smaller DRAM transistors towards the end of the decade. Instead, Micron intends to introduce wafer bonding with its upcoming 1ε DRAM process technology and adopt High-NA EUV lithography for subsequent generations. Meanwhile, the company is developing new types of memory, including vertical high-bandwidth memory (vHBM) and vertical edge inference memory (vEIM), which will be integrated directly on top of processors.

"DRAM is nearing atomic limits at this point," said Scott DeBoer, president and chief technology and products officer at Micron, during the company's event this week. "Although we have confidence in several more planar nodes, we are very focused on making sure that we introduce 3D DRAM at the optimal time from a cost and performance point of view."

Wafer bonding, High-NA EUV, and new materials

Micron's current 1γ DRAM process is already in high-volume manufacturing, whereas its successor, 1δ, is scheduled to enter volume production in the second half of 2027. The latter promises a mid-20% increase in bit density and is optimized for future AI memory products, including HBM5, vHBM, and vEIM. Beyond 1δ, Micron plans to introduce wafer bonding with its 1ε process, which is currently under development. However, the company has not disclosed how it intends to implement wafer bonding or what improvements it expects from the technology.

For subsequent generations — ζÅ and ηÅ — Micron plans to adopt High-NA EUV lithography (ζÅ, zeta angstrom, Micron's 1^st Generation sub-10nm-class DRAM node) and new materials (ηÅ, eta angstrom, Micron's 2^nd Generation sub-10nm-class DRAM node) to continue shrinking DRAM cells. For many of its upcoming fabrication technologies that will be used over the next five to 10 years, Micron is also collaborating with Albany NanoTech. Of course, as with all organizations like Albany NanoTech, we are mostly talking about fundamental, or pre-competitive, IP that could be used for DRAM production at some point.

 "Albany NanoTech, our announced focus on advanced lithography [is] really driving High-NA EUV roadmap for DRAM," said DeBoer. "In particular at Albany with our team there, focused on the next five to ten years."

Micron is also developing 3D DRAM technologies and lists two generations — 3D1 and 3D2 — in its roadmap already. However, the company has not disclosed its architectures or launch schedules, as it intends to introduce 3D DRAM only when the technology offers sufficient advantages in manufacturing costs, complexity, and performance over conventional planar DRAM.

"When we look at three 3D DRAM we have that on the roadmap, as I mentioned, and it is shown here in between one zeta and one eta," said Micron's CTO. "But in reality, this is a parallel path, and we will implement it [3D DRAM] in a fashion that is ideal for cost, complexity, and device performance."

Going vertical, becoming critical

Beyond developing new process technologies for its upcoming DRAM products, Micron is also working on all-new types of DRAM products that are tailored for very specific use cases, including vertical HBM (vHBM), vertical edge inference memory (vEIM), and various custom HBM (cHBM) implementations.

vHBM will place memory stacks directly on top of processors (such as AI accelerators and AI GPUs) rather than next to them. This approach promises substantially lower latencies and higher bandwidth thanks to shorter connections. However, placing memory above a processor creates significant thermal challenges and limits the number of memory stacks that can be integrated on top of an ASIC. Therefore, Micron expects vHBM to complement conventional HBM, which will continue to provide the bulk of memory capacity in many AI accelerators.

Another technology under development is vertical edge inference memory (vEIM), which shares architectural and packaging characteristics with vHBM but targets different applications. Whereas vHBM prioritizes maximum bandwidth for high-performance AI accelerators, vEIM is focused on energy efficiency for edge AI processors used in autonomous vehicles, robotics, and other power-constrained devices. Nonetheless, even the 1^st Generation vEIM targets formidable 2 TB/s bandwidth at

Both vertical memory architectures will require advanced packaging technologies, particularly hybrid bonding, which enables much denser connections than conventional microbumps. Thermal management will also be critical, especially for vHBM. To meet cooling requirements, Micron is developing specialized heat-spreading structures to transfer heat from hot regions of memory base dies through the DRAM stacks.

The company has not disclosed when vHBM, vEIM, or cHBM will enter commercial production. What is important about the development of such types of memory is that it indicates that future improvements in memory performance will increasingly depend on advanced packaging and closer integration with processors, which will require collaboration between DRAM makers and logic developers. In turn, this transforms memory from a commodity to a critically important ingredient of an ASIC design.

DRAM featuring 4F² memory cells has long been considered one of the holy grails of the DRAM industry, as they promise to reduce cell area by 33% compared with conventional 6F² designs and therefore enable building DRAMs with more memory cells in the same area. However, after working on 4F² memory cells for a couple of decades, Micron has concluded that the architecture offers no meaningful density advantages, increases manufacturing complexity and costs, and has fundamental scaling limitations. This has a dramatic impact on Micron's future plans.

"Micron invented 4F² DRAM," said Scott DeBoer, president and chief technology and products officer at Micron, during the company's event on Wednesday. "The path with 4F² DRAM is always been an option through time, and we have evaluated it and not pursued it due to increased complexity and cost through this past two-decade period of time."

Interestingly, both Samsung and SK hynix still have 4F² memory cells in their roadmaps (according to TechInsights), so Micron's rejection of the technology puts the company on a unique trajectory. Several years ago, the company delayed integration of EUV lithography into its manufacturing flow, contrary to what its rivals did, and still managed to retain competitive positions both in terms of costs and in terms of performance. Therefore, skipping 4F² memory cells is not completely surprising.

4F² is not the future of Micron's DRAM

The main attraction of 4F² DRAM is its theoretically smaller memory cell. The 4F² naming refers to a cell area equivalent to four times the square of the minimum lithographic feature size (F), compared with six times F² for conventional DRAM.

At identical feature dimensions, a 4F² cell occupies approximately 33% less area than a 6F² cell, which could theoretically increase the number of memory cells per wafer by 50%. Such an improvement would reduce manufacturing costs per bit and increase per-device memory capacity even without an equivalent reduction in feature dimensions. However, to make these advantages possible, DRAM makers must develop a suitable transistor architecture and a sufficiently compact capacitor arrangement. This is not easy at all.

The CTO of Micron says that the theoretical advantages of 4F² DRAM do not necessarily translate into higher memory density in practice. DeBoer explained that dimensions and pitch of DRAM capacitors, rather than the nominal area of DRAM transistors, ultimately determine how many memory cells can fit on a wafer. Both 4F² and 6F² transistor structures must fit beneath the capacitors, which means that reducing transistor area alone does not guarantee a corresponding reduction in overall cell size because transistors need a capacitor. Furthermore, Micron believes that 4F² introduces additional manufacturing steps and complexity that increase costs without delivering sufficient benefits.

"It is important to understand the capacitor pitch, the capacitor size, and dimensions, is what sets the DRAM bit density, not whether it is 6F², 4F², 8F²," DeBoer said. "From our investigation of this technology over the past couple of decades, it is a bit of a myth that 4F² actually provides anything versus 6F². It is capacitor pitch that defines the DRAM. You can build the cells, the transistors underlying them in different ways, but they still have to fit under the capacitor pitch, which sets the DRAM [cell size]. So, some of that is just smoke and mirrors in terms of talking about 6F² versus 4F²."

4F² memory cells may curb new process technologies

Instead of adopting the 4F² DRAM cell architecture, Micron plans to continue scaling conventional 6F² DRAM. The company believes it can increase bit density by reducing capacitor pitch and shrinking process technologies even without introducing a fundamentally different transistor architecture.

Advanced lithography, new materials, and wafer bonding should allow Micron to extend planar DRAM scaling for several more generations, according to the company. For example, its upcoming 1δ process technology, scheduled to enter volume production in the second half of 2027, promises a mid-20% improvement in bit density compared with its predecessor. Micron also plans to adopt High-NA EUV lithography for future DRAM generations.

Interestingly, DeBoer fully acknowledges that 4F² DRAM is technically feasible and that Micron itself has manufactured experimental devices based on the architecture. However, its manufacturing complexity and costs become increasingly problematic as feature dimensions shrink, so essentially Micron claims that it can either adopt 4F² or use more sophisticated process technologies, a claim that perhaps implies why China-based CXMT recently praised 4F². Although DeBoer did not identify any specific physical limitations involved, he stated that 4F² has no sustainable scaling path beyond a certain point. This suggests that Micron sees little value in introducing an intermediate architecture that would eventually require another major transition.

"When you look at a scaling path, you can go back a few nodes and absolutely, 4F² can be built back a few nodes, no question about it," DeBoer noted. "It is more complicated, it is more complex, it is more costly, but you can do that. When we look at scaling 4F² beyond where we are sitting today, there it is; it is physics. There are fundamental problems with 4F² scaling that ultimately will lead to 3D DRAM coming in instead of 4F²."

3D DRAM is the future

Indeed, Micron's preferred long-term solution is 3D DRAM, which would increase memory density by stacking memory cells vertically rather than relying exclusively on reductions in their lateral dimensions. Alongside development of multiple next-generation planar DRAM process technologies, the company is already developing multiple generations of 3D DRAM production nodes (which is not surprising, as 3D NAND nodes will rely on fundamental innovations developed for planar processes), although it has not disclosed when the new architecture will enter commercial production. DeBoer indicated that Micron will make the transition when 3D DRAM offers the right combination of density, manufacturing complexity, and cost.

Although both Samsung and SK hynix have 4F² DRAM products in their roadmaps, Micron believes that the assumption that reducing the nominal footprint of DRAM cells improves manufacturing economics is wrong and that extending 6F² scaling and eventually adopting 3D DRAM offers a better long-term strategy.

The two biggest NAND flash memory manufacturers on the planet, Samsung Electronics and SK Hynix, are reportedly working to upgrade their Chinese factories to produce more advanced chips for use in AI data centers, Reuters reports. The move comes as the two companies continue to fight off competition from the fast-growing Chinese memory makers like CXMT. Fierce competition in the lucrative AI RAM market has already seen manufacturers slash consumer-focused production to allow them to increase production capacity for the more advanced — and money-spinning — components.

Citing four people familiar with the companies' plans, the report claims that Samsung Electronics aims to switch its Xian plant to the production of 286-layer flash chips by the end of the year. SK Hynix has its sights set a little lower, targeting chips with 240 or more layers at its Dalian facility. That factory was taken over back in 2021, but a timescale for the new upgrades isn't clear.

However, while Samsung Electronics and SK Hynix are well placed to deal with the growing threat from Chinese chipmakers, both are faced with additional complications in the form of U.S. regulations. Export controls on chipmaking equipment were applied in 2022, with the aim of slowing China's technological progress. Both companies, based in South Korea, must now get licenses in order to install U.S.-built hardware in Chinese factories. The report points to this as a reason for the recent growth of Chinese firms like Yangtze Memory Technologies Co. (YMTC). The company told investors at a recent IPO preparation meeting that it aims to become the world's largest NAND flash producer by the end of 2027.

While both Samsung Electronics and SK Hynix say that they are working in consultation with the U.S. authorities, there's little doubt that this extra step has hampered the companies' ability to upgrade their factories to better meet the new AI memory demand.

It's impossible to overstate just how key Samsung and SK Hynix are to NAND supply. Samsung's Xian factory produces around 40% of the company's global output. It currently produces chips that have around 200 layers, but Samsung's plans aim to boost that to 286 layers for V9 NAND chips. For its part, SK Hynix's Dalian plant currently produces chips with 192 layers, with the company's aim for 240-layer chips reportedly confirmed by three people familiar with the plans.

Meanwhile, CXMT, China's premier chipmaker, is looking to move beyond DRAM production. A report from September 2026 noted that it was eyeing production of 3D NAND memory for use in solid-state storage (SSD) products. The country's largest DRAM producer, CXMT, posted $22.41 billion in revenue and $11.57 billion in net profit in the first half of 2026 after years of losing money. But despite this purple patch, the company is still much smaller than the likes of Samsung, SK Hynix, and Micron.

Micron faces a one-day labor stoppage at its Taoyuan operations in Taiwan on October 22, Reuters reports. Micron's employees are striking for concrete terms for this year's bonus and a clearer mechanism for sharing the company's future profits. The strike's teeth come from the resultant financial impact on Micron's operations, as semiconductor fabs are supposed to operate around the clock. The scheduled protest comes amid strong demand for memory chips and will have a minor impact on Micron's memory output.

The Taoyuan union wants Micron to present a specific proposal for this year's additional employee bonus and establish a transparent formula for distributing a portion of future profits. Previous negotiations between the company and the union ended unsuccessfully in September, which prompted employees to approve industrial action in early October. Nonetheless, the union stresses that the October 22 strike is intended to pressure Micron into reaching an agreement rather than terminate negotiations. The union is prepared to conclude a deal if the company presents terms acceptable to employees across its Taiwanese operations.

The situation could become more serious if employees at Micron's Taichung operations, its largest manufacturing site in Taiwan, decide to join the action. A separate labor organization that represents workers at that facility is scheduled to meet with Micron for mediation on October 22, the same day as the Taoyuan protest. However, the Taichung union has not yet authorized a strike.

Micron's fabs in Taiwan produce commodity DDR5 and LPDDR as well as expensive high-bandwidth memory (HBM) for AI accelerators. Amid record demand for memory of all types, even a one-day suspension of operations would have a material impact on Micron's output and earnings.

Modern semiconductor fabs are supposed to work 24/7/365, as many processes cannot be halted. However, if management has sufficient time and personnel to prepare, a one-day warning strike does not necessarily mean a complete shutdown of Micron's Taoyuan manufacturing operations, not to mention permanent damage to wafers or equipment. The actual consequences of the strike will depend on employee participation, which manufacturing operations are affected, and Micron's contingency plans. While it is likely that the output will drop, the decline will likely be negligible.

Micron employs approximately 15,000 people in Taiwan. The workers point to compensation arrangements at Samsung Electronics and SK hynix as examples of how semiconductor manufacturers can distribute profits among employees as AI-driven demand generates unprecedented cash flows for memory firms.

What if you could buy a cheap used DDR5 SODIMM (laptop memory) kit and transform it into a super-fast DDR5 desktop kit? That’s what electronics hobbyist Blighted Agent recently did when they succeeded in converting a SK hynix 2x 16GB DDR5-5600 SODIMM kit they got from Facebook Marketplace for $120 into a 2x 16GB DDR5-7800 desktop kit, claimed to be worth around $1,000. They also had to buy some blank DDR5 desktop memory PCBs from AliExpress for around $16 each, and a set of heatsinks for around $18.

In the above video, our hero says they bought the donor laptop 2x 16GB DDR5-5600 sticks for just $120, which is a bargain. With extra bits and pieces from AliExpress (desktop DDR5 PCBs, etc.), the total bill of materials came to $175. Blighted Agent comments that the SODIMMs used what he believed to be SK hynix A-die modules, which are the same as the ICs used in expensive desktop DDR5 modules like the G.Skill Trident Royal line.

The process began with taking the memory ICs from the donor modules using a hot air station. Then they were cleaned and had 0.45mm leaded solder balls added, using a DDR5 stencil, reballing jig, and hot air. Next, the blank desktop DDR5 PCBs were prepared. A little solder was added to the plethora of BGA connectors to be ready for the memory chips to connect to.

The old DDR5 ICs and the new desktop modules could now be mated, using flux, the preheater, hot air, and watching and prodding carefully with a dental pick. Blighted Agent’s experience lets him know when the BGA chips have successfully mated with the PCB. You can eyeball when they pop precisely into place due to surface tension, and offer up a modicum of resistance to pick prodding.

Finally, the enthusiast added the SPD chip and BIOS chip from the SODIMMs to the new desktop DIMMs. These new desktop DIMMs were quickly tested in a PC before they were finished off with carefully applied thermal pads and the fancy-looking heatsinks.

Blighted Agent felt lucky that there were no issues with the newly created desktop modules. There’s a lot of intricate things that can go wrong during such a process. The initial boot verification showed them recognized in his Asus ROG Maximus Z790 Apex Encore motherboard as two “SK hynix 16,384MB 5600MHz” modules, which was correct. Some tuning resulted in rock-steady performance at DDR5-7800 CL38 and 1.40V. This was verified by stress testing for 90 minutes, which the enthusiast reckons was ample for a gaming PC. It is very likely a better result than using those mechanical SODIMM-to-DIMM converters you can buy, which can be problematic.

Blighted Agent seems to specialize in BGA soldering work, and has also successfully upgraded several graphics cards with double the VRAM. Though videos like this are edited to be brief, and they make the process look easy, the TechTuber admits there is a lot that can go wrong during this kind of rework. Moreover, with RAM modules, they lack the testing equipment to locate an issue with any particular IC on the PCB. So, if this module didn’t work, they might have ended up in a world of pain, not knowing which memory chip had an issue due to either an internal fault or a BGA soldering glitch.

Looking around at used DDR5 SODIMMs, it looks like Blighted Agent was very lucky to get a used working 32GB kit for $120. I just checked eBay U.S., and the best deal there was $320. Meanwhile, the best price for a new 32GB DDR5-6000 kit seems to be $449 at the time of writing.

We reported on Russian enthusiast VIK-on succeeding in a similar project earlier this year, but all their costing was in Rubles, and they went the extra mile in flashing custom firmware so the remade modules would be auto-detected with 6400 MT/s XMP support on most motherboards. In late 2026, DDR5 RAM continues to be too expensive.

Are you looking to buy RAM for an upgrade or an existing PC? You've no doubt seen the news about the extortionate price rises on RAM and storage, thanks to the ongoing AI boom ruining the component market for PC enthusiasts; well, today, we have some slight light in the darkness, with a $108 price cut on some DDR5 memory from Corsair. You can pick up 32GB of Corsair Vengeance RGB RAM (DDR5-5600) for $409 direct from Corsair. I've checked against our own price tracking info and used various other online resources to confirm that this is indeed the cheapest available to purchase memory kit with these speeds.

● Check out this deal at Corsair

This 32GB kit comprises two 16GB matched memory sticks, both with RGB lighting running along the spine of the heat shroud. The Corsair Vengeance RGB RAM is DDR5 with speeds of 5600 MT/s and a CAS latency of 40. This kit comes with Intel XMP profiles that can be selected in the BIOS.

We can't compare prices of RAM now to those of even a year ago. That's just unrealistic in the current AI economic climate, and whether you love or hate AI, it's not going anywhere soon; the rollouts of large data centers and manufacturers focusing resources on profit-heavy AI component production will continue for the foreseeable future.

There's no denying that RAM prices are tough right now. All the signs point to prices going up even further as scarcity becomes more of an issue for anyone wanting to build a PC in the next few years. If you're waiting for a fall in price, or the AI bubble to burst, you could still be waiting for up to a decade for memory and RAM production to normalize to anywhere near previous figures.

If you desperately need RAM now, this is one of the better prices on a 32GB kit. There are faster memory kits available, but you have to, of course, pay more for them, and the performance upgrades in most situations won't even be perceivable for the average user.

Elon Musk has criticized memory makers for what he calls 'extortionate' pricing amid an unprecedented shortage of both conventional DRAM and high-bandwidth memory (HBM). Although Musk did not identify the companies he criticized, his remarks seem to be directed at Samsung Electronics and SK hynix, as he praised Micron for its more 'reasonable' approach at the same time. Interestingly, Micron also enjoys exceptionally high profitability: its latest quarterly gross margin reached 81%.

"Micron has been reasonable regarding future memory prices, while others have been extortionate, which is something today's customers will not forget," Musk wrote in a post on X. "Micron is making the smart move for long-term customer loyalty."

Musk did not provide specific details of said extortionate pricing or disclose terms offered by different memory suppliers (which tend to be confidential). Consequently, it is impossible to determine whether Samsung and SK hynix charge substantially more than does Micron for comparable products. Nevertheless, Musk's remarks suggest considerable frustration with the pricing policies of South Korean memory manufacturers.

Over the past several quarters, memory has transformed from an easy-to-obtain commodity to a strategic asset, and makers of 3D NAND and DRAM have certainly benefitted massively from this shift. Historically, memory makers have responded to strong demand and rising prices with aggressive capacity expansions, which eventually led to oversupply and falling prices. This time around, however, manufacturers have raised memory prices severalfold without comparable increases in production capacity. As a result, supply still lags behind demand and will continue to do so for years to come, which puts further upward pressure on memory prices.

What makes Musk's praise of Micron particularly interesting is the company's financial performance, which clearly suggests that the company is taking advantage of the situation in the market. In its fourth quarter of fiscal 2026, Micron reported revenue of $54.23 billion and a GAAP gross margin of 81%, up from 40% a year earlier. The company's cloud memory unit earned $16.283 billion, and its non-GAAP gross margin totaled 83%; its core data center storage business sold goods worth $18.002 billion with a 90% gross margin; while sales of the automotive and embedded units totaled $6.824 billion with gross margins reaching 84%.

Perhaps the most surprising part of Micron's last quarter report was its mobile and client revenue of $13.114 billion and non-GAAP gross margin of 90%, which means that Micron earned higher profit selling memory and storage for client devices than it did for selling memory solutions for data centers. Such results clearly indicate that even supposedly reasonable memory prices can generate extraordinary profits in the current market.

Memory manufacturers are increasingly shifting toward long-term supply agreements (LTAs) that guarantee future supply and provide customers with predictable prices of DRAM, HBM, and NAND. So far, Micron has signed 26 strategic customer agreements that cover more than 35% of its expected revenue through 2030. These contracts include $32 billion in customer financial commitments, most of which consist of cash deposits. The company acknowledges that its new agreements reflect higher prevailing memory prices, and it by no means is trying to sell memory at a discount.

Samsung has reportedly secured long-term contracts covering 75% – 80% of its planned memory output in 2027, according to South Korea's ⁠Korea Economic Daily (via @Jukan05). SK hynix is reportedly pursuing similar arrangements as AI infrastructure investments continue to absorb available memory capacity.

Market insiders and analysts expect memory supply shortages to persist through at least 2028, and that gives manufacturers considerable leverage in contract negotiations. Memory suppliers have little incentive to reduce prices and are eager to enjoy their position, but Musk's warning suggests that today’s pricing policies could influence customer relationships once supply and demand eventually return to balance.

The AI-induced PC component shortage, which has caused drastic increases in the cost of DIY building, continues to get worse. Since last year, RAM prices have increased by more than 500% and show no sign of slowing down. In August, we reported that DDR5 6000 RAM — the sweet spot benchmark for both performance and pricing — had reached $400; now, the price is $450.

• Save by going slower: CORSAIR Vengeance RGB 32GB (2 x 16GB) DDR5 5200 - $399 at Newegg

As mentioned, because DDR5 6000 RAM is a de facto standard configuration and capacity in terms of performance, tracking the price of this particular spec has proven to be a strong barometer of the industry overall. While we track RAM prices across multiple models and kits, we also track the price of 32GB DDR5 6000 RAM daily.

We've been creeping closer to $450 for some time. As of today, the cheapest 32GB DDR5 6000 kit on the market costs $449.97, or three cents shy of $450. Cheaper RAM is still available; this 32GB DDR5 4800 kit is $399 at Corsair, but good, speedy RAM is now harder to buy than ever before. The 4800 Corsair kit once cost just $80.

As RAM prices and other component hikes have a knock-on effect on PC pricing as a whole, it was recently reported that PC shipments in 3Q26 have tumbled by a massive 20%, with the top three vendors shipping 11.6 million fewer units than the same period last year.

Combo deals remain a rare bright spot. Various Newegg bundles could save you as much as $358 when you buy RAM alongside a motherboard, CPU, and even an SSD, and we've seen a recent resurgence in stock on these.

Pre-builts also continue to offer some solace to wannabe DIY builders, with price hikes trickling down to systems more slowly. With industry figures warning that memory shortages could persist well into next year, or even last up to a decade, in the space of just 12 months RAM has gone from being a PC gaming commodity to a luxury few

CXMT expects to launch its first 4F² product, a server DDR5 RDIMM, by the end of the year, company president Cao Kanyu said in remarks reported by Yicai. The memory will be built on a denser cell layout, not yet commercialized, using vertical transistors to reduce the cell’s footprint by about one-third on paper. No speeds or capacities have been announced yet for the new product.

Cao spoke about the new RDIMM at the Integrated Chips and Chiplets Conference on Saturday. A 4F² cell is 2F by 2F at about two-thirds the area of current 6F² cells at the same feature size, and designs so far all stand the transistor up. The company has produced research and patent filings on the technology with papers in 2021, 2023, and 2025, and an 8Gb full-array research example was demonstrated at IEDM 2023.

Cao said CXMT’s version, the Vertical Surrounded Gate (VSG) transistor, has a channel that stands vertically with the gate wrapped around it, allowing stronger gate control with less leakage. Most importantly, standing the transistor up shrinks the cell. CXMT now has more than 300 published patent families tied to 4F², he added. The report says the industry as a whole is moving toward 4F² with 3D solutions that decouple DRAM and CMOS processes, combining them with wafer-level hybrid bonding, which allows logic and cell density to be optimized independently. Cao also covered CXMT’s own hybrid-bonding work, which began in 2019, with published patents.

Aside from this announcement, China’s primary DRAM maker has been in the news lately for its manufacturing and market-share gains. Its fifth-generation G5 DRAM technology platform, announced Sept. 20, is in mass production. TrendForce puts CXMT’s share of global DRAM revenue at 9.5% in the second quarter, up from 7.6% in the first, good for fourth place. Last November, CXMT showed off DDR5-8000 and LPDDR5X-10667. It has revealed itself as a manufacturer to be taken seriously by the biggest existing players.

Samsung showed off a 16Gb, 10nm-class 4F² DRAM design in its ISSCC 2026 paper in February. That one also used vertical-channel transistors (VCT), with the array bonded on top of the periphery using wafer-to-wafer hybrid copper bonding. The company claims the bonding raises dies per wafer by more than 20% with the same design rules. In April, The Elec reported that Samsung had a working 4F² VCT die on its sub-10nm “10a” process, with mass production targeted for 2028. Later South Korean reports clouded that date: the VCT version has since been split off as “D0a-V” with no timeline, and there is no firm timeline for adopting 4F².

SK hynix laid out plans at VLSI 2025 for a 4F² vertical-gate platform and 3D DRAM at nodes of 10nm and below, with circuitry bonded under the cell array. The April report also puts SK hynix’s 4F² debut at the 10b node, one step after Samsung’s 10a. Micron’s plans remain less clear, with no widely reported 2026 statement.

The announcement is perhaps more interesting for what wasn’t mentioned: capacity, speed, die density, process node, named customers, or intended volume. All we have is a date and a purported cell design, admittedly well-supported by the literature, but no product that has been tested by anyone outside of CXMT. Beyond Cao’s talk, CXMT hasn’t posted a release about the product in its Chinese or English newsrooms.

South Korean reports have said that CXMT’s initial products may only partly use 4F² and that producing stable units at volume is a separate challenge. With about 11 weeks left in the year, it will be interesting to see what CXMT actually delivers.

If you're in the market for a deal on DDR5 RAM during the Amazon Prime sales, Corsair might have the answer with a sale on 32GB of DDR5 5600 memory. Right now you can save $103 and grab this kit for $414.99.

• Check out this deal at Corsair

This is obviously a lot more expensive than the RAM prices from a year ago, but it's as good as it gets in today's market, with prices continuing to rise and showing no sign of letting up anytime soon. The cheapest DDR5 6000 kit — the sweet spot for AM5 gaming — is $437. For slightly more modest speeds, this is a decent saving, and the cheapest kit of this capacity and clock on the market. Crucially (pun not intended), this kit supports both AMD EXPO and Intel XMP, so will work with either platform for best speeds. If your rig runs with an Intel CPU, you can save $5 more with this kit.

There's no denying that RAM prices are tough right now. Unfortunately, all the signs point to things getting worse, rather than better, with some industry figures suggesting the RAM shortage could last an entire decade.

If you need RAM right now, either for a new build or to upgrade your existing system, then this is about as good as it gets.

Corsair is actually hosting a RAM sale across lots of its products, with savings of up to 30%. Prices remain high, but you can check out the whole sale here.

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Also, you can join the Tom's Hardware deals Discord for up-to-the-minute hardware deals.

A YouTube channel best known for its skillful graphics card fixes has published its first RAM module repair video. Tony from NorthWestRepair’s latest video shows his attempts to mend a pair of high-capacity DDR5 sticks worth a purported $16,000. It isn’t the repair skills that are newsworthy here. Rather, it’s the shift in economics that makes the chuck-it-and-replace-it attitude to bad RAM a philosophy that simply doesn’t apply in 2026. The impact of the AI-pocalypse means that spending a couple of hundred dollars on repair labor to save a several-thousand-dollar DDR5 DIMM is now sensible. If you can repair RAM, you can now start a business.

Two DDR5 sticks were sent in to Tony, described as having physical damage. They are both ECC sticks, meant for servers, one with 128GB and the other with 256GB of DRAM ICs onboard. Tony sounded happy at the start of the video, as this is an excuse to use his Unified DDR Flasher Main Board, for which he had just acquired an RDIMM extension that works with these server sticks.

Initial close physical inspection didn’t reveal any conclusive evidence of the source of the problems. So, it was hoped electrical tests would provide more clues. A data line tester didn’t highlight any issues, though. Tony used flux and hot air to reflow the solder on the first DIMM, which is a far simpler process than a reball (where all the memory ICs are taken off, cleaned, and given new solder balls). Initial signs were that the module was now working OK. So, he moved to the next DDR5 DIMM.

The second DIMM “may have a faulty PMIC chip,” which is why it seemed more severely broken than the first module, Tony indicated. Powering on a system with this DIMM inserted showed no signs of life, and the DIMM didn’t even warm up (thermal camera checks). That contrasts with the first fix.

Because this DIMM is completely dead, Tony did some work on the non-DRAM chips like the PMIC and SPD EEPROM first. Then he decided to reflow some other chips, including memory ICs, like before, while the board was warm. Some ICs were also reballed after inspection, making Tony suspicious of them.

The repairer found a short circuit via voltage injection and thermal camera monitoring. This was fixed with a new capacitor and by fixing the short on the damaged edge of the PCB. Finally, a new PMIC chip ended the quest, and this second DDR5 DIMM powered on and trained successfully.

The repair is good to see, saving these valuable components from e-waste. However, the bigger picture is that repairing memory modules could now be a viable business. Previously, it didn’t make sense to spend a hundred or two on labor to fix a DIMM that would cost about the same or even less to replace with a new one. Now the repair fee might be just a fraction of a replacement price.

Micron released its fiscal Q4 2026 financial results on Wednesday, expectedly setting another record for revenue with $54.23 billion for the quarter, up nearly five times since the same period last year. Micron also hit a record 87% gross margin, the largest contributor to which was Micron's Mobile and Client (consumer) business unit. Further, Micron's client business was the only one that shipped less memory last quarter, despite bringing in the highest operating margin at 88%.

Micron's margins overall are up significantly year-over-year; Core Data Center surged from 25% to 85%, and Automotive and Embedded have climbed from 20% to 79%. The Mobile and Client unit also saw significant growth, with a 29% operating margin in fiscal Q4 2025, and now a margin of 88%. Cloud Memory margins grew, though not to the same extent as other units, moving from 48% to 76%.

The gross margins are interesting to look at, too. In a financial statement, the gross margin equals revenue minus cost of goods. Operating margin, on the other hand, equals revenue minus cost of goods and all other operational expenses. The operating margin simply excludes taxes and interest.

The gap between gross and operating margin is what's interesting in the breakdown above. The Mobile and Client unit has the smallest gap, with only a 2% difference. The Core Data Center unit matches the Mobile and Client unit with a 90% gross margin, but it has a lower operating margin at 85%. In other words, the cost of running Micron's consumer business is extremely low relative to the amount of revenue it currently generates.

It also saw the lowest amount of growth for the quarter, with revenue up 14% quarter-over-quarter. Micron says this was "driven by higher pricing, partially offset by lower bit shipments." Out of Micron's four business units, the Mobile and Client unit was the only one that shipped less memory in the past quarter.

For clarity's sake, a bit shipment is just a shipment. Micron measures shipments in bits rather than units. It's the capacity Micron has shipped in a quarter, not the actual number of DRAM or NAND chips.

Outside of Mobile and Client, Micron attributes higher revenue to higher pricing and bit shipments. The situation in the Mobile and Client unit echoes a sentiment we've heard elsewhere: growth in the consumer market is still happening, but it's driven by higher pricing, not growth in shipments.

Earlier this year, Intel's David Zinsner, chief financial officer, attributed a 13% YoY growth in Intel's consumer business to higher average selling price (ASP), not increased unit sales. Zinsner clarified that Intel "thought we had seen some inflation on our cost and needed to pass that on to the end customer."

Micron's outlook for fiscal Q1 2027 has revenue set at another record of $61.5 billion ± $1.5 billion, with gross margin rounding from 87% in fiscal Q4 2026 to 86.25%.

Another record quarter signals more squeeze on the DRAM and NAND markets. Echoing rival SK hynix, Micron says it expects memory and storage to be "much tighter" in 2027 and 2028, claiming that the company expects the industry to be supply-constrained in both years. That's despite a growth in supply that Micron anticipates.

The company says it expects industry NAND bit shipments to grow in the mid-20% range, and DRAM bit shipments to grow in the low-20% range. The industry broadly will produce more memory over the next two years, says Micron, but that still won't keep pace with demand.

Worrying still is this line in Micron's earnings slides: "we do not have line of sight to when supply and demand will return to balance." However, the company says it plans to increase its capital expenditure (capex) in fiscal 2027 compared to its prior estimates.

A "majority" of that increase is set aside for construction of additional clean room space, which Micron has set for 2028 through the end of the decade. Hopefully, that additional clean room space coming online will ease supply constraints, but we're still a long way from that point.