Huawei has introduced its first desktop PCs powered by its own 10-core processor as well as proprietary HarmonyOS operating system, reports the Southern China Morning Post. The company claims that the CPU and the OS are built entirely of using 'components manufactured' in China, which matters when it comes national security and domestic supply chains inside the sanctioned country. But whether these machines are truly 'entirely domestic' is an open question.

The Huawei Qinyun HM650 and HM650g desktop PCs come with 16 GB of LPDDR5 memory (probably made by China's CXMT) and either a 256GB or 512GB SSD (probably made by Chinese flash maker YMTC) are powered by the company's Kirin X90 system-on-chip, which originally debuted in Huawei's consumer systems in 2025. The key ingedient of the system it its processor, which features 10 Huawei-designed Armv8-based Taishan CPU cores in a 4+4+2 configuration, with all cores supporting simultaneous multithreading (SMT) to execute up to 20 threads simultameusly. The chip also integrates Huawei's Maleoon graphics processing unit (Arm Mali-based) and a dedicated neural processing unit for AI workloads.

Although Huawei doesn't officially disclose the Kirin X90's manufacturing process, a teardown analysis by TechInsights confirmed that the CPU is manufactured by SMIC using its 7nm-class N+2 process technology. This makes the X90 an example of Huawei's ability to develop PC-class processors using domestically available semiconductor manufacturing capabilities, albeit on a process technology that trails leading-edge nodes from Intel, TSMC, and Samsung.

The most interesting aspect of the Qinyun HM650 series is certainly Huawei's claim that all of its new system's components, including the processor, memory, storage, power supply, and wireless connectivity are manufactured domestically. Such certification itself does not necessarily mean that the entire semiconductor supply chain behind the machine is Chinese. While the CPU, memory, and storage chips are fabricated domestically, they are still made using foreign manufacturing equipment (from the Netherlands, U.S., and Japan), materials (from Japan), intellectual property (from the UK), and electronic design automation (EDA software from the U.S. and partly from China) tools.

Meanwhile, the claim about the operating system developed in China sounds ambitious. The machines run Huawei's HarmonyOS Enterprise Edition, which certainly reduces their dependence on foreign technology suppliers. Unlike conventional PCs that rely on Microsoft's Windows operating system, Huawei's desktops use a software platform developed and maintained by a Chinese company. Furthermore, unlike earlier HarmonyOS versions that incorporated Linux components, the HarmonyOS Enterprise Edition uses Huawei's own kernel and software architecture. This indeed gives Huawei greater control over operating system development, security updates, and integration with its hardware, although compatibility with existing Windows applications could remain a limitation for enterprise customers that rely on software by multinational corporations for Windows.

Keeping all these things in mind, can we say that Huawei's Qinyun HM650 series relies entirely on components developed and made in China? Probably yes. Yet, with major caveats, including a semiconductor supply chain that relies on tools and software designed and produced elsewhere. Furthermore, incompatibility of the OS with software designed for Windows could be a limitation for some customers.

A security researcher has revealed how they were forced to update the time on their car infotainment system using reverse engineering techniques. Of course, invasive tech surgery shouldn’t be needed for this kind of basic routine daylight saving time tweaking task. However, Rasmus Moorats’ 2014 Renault Latitude wouldn’t allow him to adjust the time because the original navigation map SD card was missing.

Moorats had been warned. When he bought the used car, the previous owner noted that the SD card would be required to change the time on the in-car display. “I didn't really find that believable,” recalls the security researcher. They seem to have believed it was a skill issue of the prior owner and, because the maps it contained were chronically out of date, they decided to confidently decide they didn’t need the SD card...

The time to adjust non-connected clocks to daylight saving time inevitably came, and Moorats decided to adjust the in-car time display, which had become an hour out of sync. Two settings menus were available via the in-dash system. One allowed the adjustment of Bluetooth and Phonebook settings – clearly no use here. But the second settings menu wouldn’t produce any submenu. Instead, an error message "No maps detected!" popped up every time it was prodded.

With a certain set of skills under his belt, Moorats decided to “just RE it,” where RE = reverse engineer. He found out that the head unit ran a customized Linux-based TomTom operating system on a Samsung SoC. In brief, he extracted and analyzed the firmware, built a QEMU environment for the device, reversed the scripting engine, and uncovered a number of vulnerabilities affecting the system.

The breakthrough came in a brainwave, which seems to stem from experience with kernel exploit techniques during his day job. “Instead of trying to get the userland to execute our script, why don't I get the kernel to execute our script instead?” pondered Moorats. The approach worked, rewarding Moorats with root-level access to the infotainment system.

The 2014 Renault Latitude owner subsequently discovered that the date & time settings were in /mnt/flash/settings.dat in a custom binary format. Interestingly, the system “doesn't really have a concept of time zones at all,” observed Moorats in the conclusion of his blog post. “It gets the time from GPS and stores the local offset as a number of minutes. Mine was set to 180. I changed it to 120.”

Ukraine is developing a new class of combat robots designed to operate inside underground gas pipelines, where Russian troops have repeatedly attempted to bypass frontline defenses, United24Media reports. The project, disclosed by Ukraine's 2^nd National Guard Corps, Khartiia, involves modifying unmanned ground vehicles (UGVs) to perform reconnaissance and combat missions in spaces too narrow for conventional military machinery. Notably, the work is being carried out by specialists from the corps’ Lava Unmanned Systems Regiment, following Operation Veles — an underground assault that saw Ukrainian soldiers advance more than 15 kilometers through pipeline infrastructure near Kupiansk. Khartiia says the operation killed more than 100 enemy soldiers and resulted in over 30 captured, although those battlefield figures have not been independently verified.

The commander of Lavas ground robotic system battalion, identified by the callsign ‘Matematyk’, said the project addresses a category of warfare that requires a different approach from conventional battlefield robotics. “There is a very long list of tasks that need to be accomplished to fight underground and counter the enemy underground. This is a new class of technologies and challenges that we will have to confront,” he said.

The machines are being adapted from existing groundrobots,rather than developed as conventional surface vehicles. They must be compact enough to navigate narrow pipelines while retaining the ability to carry out military assignments . Most commercially available underground machinery, meanwhile, is designed for construction, drilling, and tunneling — not combat.

As of now, Khartiia is already developing several robotic systems to address those limitations, with the broader objective of sending machines into dangerous underground environments where soldiers would otherwise have to conduct reconnaissance, confront enemy positions, clear positions, or clear out themselves. “War is already underground, and it will expand. The question is how we adapt to this war,” Matematyk said.

The project follows unusual battlefield developments near Kupiansk, where Ukrainian forces used the same underground infrastructure that Russian troops have previously exploited to infiltrate behind Ukrainian defensive positions. During Operation Vels, Ukrainian soldiers moved through a gas pipeline measuring approximately 1.2 meters in diameter, according to a report by Ikrainska Pravda. The confined passage made movement and close-range firefights particularly,with Ukrainian troops having little-to-no room to maneuver.

Russia had previously used the pipeline network beneath the Oskil River to move soldiers toward Ukrainian-held territory. The Ukrainian battlefield monitoring group ‘Deepstate' reported an earlier Russian infiltration attempt in September 2025. Last month, President Volodymyr Zelenskyy said that Ukrainian forces had eliminated more than 100 Russian troops and captured over 30 during the operation. The experience also exposed the limitation of sending soldiers into such environments. Underground operations restrict visibility,complicate communications , and leave little room for maneuvering equipment.

That said, Ukraine has increased its reliance on unmanned military systems as battlefield terrain proves complicated to navigate. In July 2024, we reported on Ukrainian forces deploying AI-controlled drones capable of independently identifying and attaching targets. The country has also been experimenting with unmanned systems that operate beyond conventional aerial platforms. In August, the US Army tested an autonomous Ford F-250 breaching vehicle, which builds on the Lancer unmanned ground vehicle program and uses a counter-drone turret to protect military operations from aerial attacks.

However, autonomous ground systems still face considerable technical challenges. Russia's Shturm uncrewed assault tanks , for instance , repeatedly lost their command connection during the Tsentr-2026 military exercise. The vehicle eventually became stuck in mud, even after organizers switched to manual driving. Russia has also tested an AI powered Shahed variant using Nvidia's Jetson Orin computing platform. The system was reportedly capable of identifying targets without relying on externally supplied coordinates.

Amsterdam police have arrested 150 to 200 protesters at a Microsoft data center site on suspicion of trespassing. According to a Facebook post by the authorities [machine translated], tools designed for breaking into the site were seized from the protesters, who were then allowed on their way to protest peacefully. However, it appears that some members of the group decided to enter the construction site “with violence” anyway, forcing the police to intervene and leading to their arrest. There were also some allegedly stolen items from the construction site found among the belongings of some of the protesters, plus damage and vandalism done to the data center site.

This protest is a continuation of the action that started last Friday, where protesters breached the Microsoft data center, which was being owned by Pure Data Centers. It is also the first of many organized by the “Stop Dirty Data Centers” coalition across Europe, with actions planned for Amsterdam, Dublin, Warsaw, Denmark, and several other cities across the continent. The Dutch publication NOS [machine translated] identified the exact group at the site today as Fossielvrij, who are against the use of fossil fuels in data centers such as the jet engines that Elon Musk installed at xAI’s Mississippi data center.

“Gas prices are going through the roof, and new houses are being postponed because of the overcrowded power grid. Yet tech billionaires like Elon Musk and Jeff Bezos are building energy-guzzling, hideous data centers,” the group said on its website. “We can take back the power of Big Tech by pressing the pause button now. Give us the opportunity to democratically decide what we do and do not use AI for, so that it is not at the expense of our living environment and everything that makes our lives beautiful. Then we look at how many more data centers are needed.”

The protest comes amid the AI data center build-out, which has been facing increased opposition across the United States. A Google data center site in Finland is also in trouble after it cleared out around 1,300 acres worth of forest and trees without an environmental impact assessment, displacing wildlife, and leading to a criminal probe on Tuike Finland Oy, the Google subsidiary in charge of the site.

Fossielvrij’s action was supposed to be peaceful, but it appears that another group joined the demonstration and broke through the fences around the site, leading to the police confrontation. The suspects were arrested for domestic violence and then taken to a cell complex, where it will be decided if they will be detained longer. The police also said that “All suspects will be heard afterward.”

An investigation has found that addresses for two Chinese companies approved to purchase Nvidia H200 chips led to empty offices, and the receptionists at the buildings were unfamiliar with them. According to The New York Times, these companies didn’t just have empty offices; their executives are often linked to other firms sanctioned by the United States for working with and providing advanced technology to the Chinese military.

This news has revealed concerns that the U.S. Department of Commerce is simply rubber-stamping GPU export license applications instead of scrutinizing each one for potential links to Beijing. “I have a ton of concerns that neither the Commerce Department or Nvidia is doing the due diligence needed to ensure that the licensing terms are being followed,” former China director for the White House National Security Council Liza Tobin told the publication.

Many of these approved companies include well-known entities like Baidu, BYD, Tesla Shanghai, as well as ZTE, which has previously been blacklisted from the U.S. market, Alibaba, Tencent, and ByteDance. However, the outfit’s investigation also revealed approval for two relatively unknown firms: New Matrix and Maginfra. The offices for both companies were empty shells with some office furniture, and people working nearby said they’d never heard of the company or seen anyone go to the deserted spaces.

The New Matrix website also reportedly did not contain any information about its owners or its history, although public company records reveal that it was founded by Li Bin, who, along with two other primary owners, are connected to Wise Road, a Chinese private equity firm sanctioned by the U.S. for helping Beijing acquire sensitive chip technologies. Furthermore, Mr. Li chairs Tsinghua Unigroup, a tech conglomerate partly owned by the Chinese government, and owns New H3C Semiconductor Technologies, which has also been added to the Commerce Department’s Entity List for cooperating with the Chinese military.

Maginfra, on the other hand, is suspected of being linked to Inspur, which Washington has blacklisted since 2023 for supporting the People’s Liberation Army, with both companies sharing personnel, patents, and a similar government ownership structure. These two firms aren’t listed as the final users of Nvidia’s AI chips, though. Instead, they’re supposed to assemble them into AI servers, which would then be forwarded to a final user, although it’s unclear who their customers are.

Aside from these questionable non-entities, another company that received a license to purchase H200 GPUs has some suspicious links. Zhejiang Yindun Cloud Technology’s executives are reportedly related to the founder of Range Intelligent Computing Technology Group, a data center operator that has sold compute capacity to Chinese military contractors. It’s also reportedly partly operating out of a Range data center.

President Donald Trump banned the export of Nvidia AI GPUs in April 2025, even those customized to meet the performance ceiling Washington set for AI processors. The president reversed the decision late last year in exchange for a 25% cut of the sale, but it still took more than eight months for the first H200 shipments to arrive in China. Beijing’s refusal to give Chinese tech companies the green light to buy the chips for the first few months of the year caused the delay. But once China lifted its import ban on Nvidia chips, several Chinese companies applied for licenses to buy them, and The New York Times reported that around two dozen firms have already received approval, including these questionable ones.

A homelab builder on Reddit has run Moonshot AI’s 2.8-trillion-parameter Kimi K3 AI model on discontinued second-gen Optane PMem 200 memory, using a 40-core 3rd-gen Xeon Scalable CPU and not a GPU for inference. The build runs hot, and the builder’s advice is that you “treat active DIMM cooling as mandatory,” with dual 12W blower fans aimed at the modules to get temperatures under control. The project, a follow-up to a separate user’s first-gen Optane build earlier this year, runs at a sluggish 0.85 tokens per second even with 1-bit quantization.

Kimi K3 is absolutely not built for home use, in our estimation, with Moonshot AI recommending data center inference engines to run it, and even the smallest community quantization needs at least 610GB of RAM. Using secondhand Optane, instead, is one of the few ways to reach that capacity at home. It doesn’t help that DRAM prices have skyrocketed, and the builder says the Optane memory costs “a fraction” of the equivalent.

Intel launched its Optane Persistent Memory 200 Series (PMem 200) in 2020 for its 3rd-gen Xeon Scalable CPUs in 128GB, 256GB, and 512GB capacities. On two-socket Xeon platforms, it runs at a higher effective MT/s rate than the first generation (PMem 100) that was used on the first project, and it can deliver an average of up to 32% more memory bandwidth. Optane can run in either Memory Mode or App Direct Mode; both builds had platforms allowing for each.

Memory Mode has the Optane act as system memory with DRAM as its cache, the method used in the first build, while App Direct exposes Optane as a separate, persistent region that the software maps directly, the mode used in the second. This can give “more control over where the model’s tensors live,” according to the first build’s creator, u/APFrisco, who planned to try it.

Performance does take a hit by going with Optane over DRAM, and with the higher 3-bit quantization, the speed went down even more to 0.75 tokens per second. One commenter points out that this is very slow, with a 50k-token task estimated to take 13 hours at about 1 token per second, but another notes that overnight batches don’t care as much about speed. Both speeds compare to the first build’s roughly 4 tokens per second, although in that case the builder had an RTX 3060 handling part of the model in addition to Memory Mode, a 2-bit quantization, and the smaller, earlier 1-trillion-parameter K2.5 model.

The latest builder also had to deal with heat output, with the Optane DIMMs getting “extremely hot” with sustained inference, creating a situation the builder says can endanger neighboring DRAM. That heat is consistent with Intel’s own specs, as the manufacturer rates the modules with forced airflow of 2.4 to 2.7 meters per second for cooling, which is what you expect to find in data centers. You might not normally have this level of airflow pointed directly at your memory sticks.

The expected operating conditions put each Optane module at 12W or 15W, regardless of capacity. If the build used four sticks, that would mean up to 60W of heat placed right next to the system memory. Throttling on these occurs at 83 degrees Celsius, with a thermal trip shutdown at 85 degrees, compared to the 85 degrees Celsius and up to 95 degrees in an extended range that typical DDR4 server memory is rated for. A lot of heat has to be removed from the system to keep things running.

The performance numbers given are pre-tuning — this means without tuning thread counts or NUMA affinity — so there is room for improvement, and one commenter also asked about using Memory Mode with DRAM caching for the most-used experts. The builder plans to add GPUs and to also load parts of the model into DRAM as a faster tier alongside the Optane, with “more benchmarks to come.”

CODE380, a radio manufacturer based in Kyiv, just built a new software-defined radio (SDR) that intercepts analog video signals that Russian drones transmit to their operators, making it easier for troops to find and intercept them. According to Defense News, the D·Vision SDR can sweep radio frequencies from 500 MHz to 8.7 GHz and convert any intercepted analog radio signal into a video feed. It has a detection range of up to six miles for signals on the 540 MHz to 6 GHz band, and up to two to three miles for higher frequencies.

Although this isn’t the first passive Ukraine-made drone detector, it’s one of the lightest models produced so far, weighing just 10 ounces or 290 grams — by comparison, an iPhone 18 Pro Max weighs about 8.78 ounces or 249 grams. Its competitors include the Vydun 7.5, which weighs around 2 pounds or 900 grams and could intercept signals at up to 7.5 GHz; the 23-ounce (650-gram) Chuyka 3.0, which can detect signals at up to 8.8 GHz; and the SENSE-4, which weighs 21 ounces or 600 grams and could detect drone signals of up to 8.2 GHz.

How much money are you willing to spend during the Black Friday sales?

All these receivers cover the 4.1 to 4.5 GHz band that Russian Molniya strike drones began using in June of this year to transmit video back to their operators, Presidential advisor Serhii “Flash” Beskrestnov said. However, he also warned against relying on them for protection alone. “Most detectors don’t see these frequencies, or see them poorly,” he said in a social media post. “I’m warning you so that trust in a detector doesn’t cost you your life.” These receivers are often designed to work in tandem with other sensors, like radar, acoustic sensors, and drone interceptors, as part of an anti-drone defense system.

Most of these units are designed to intercept analog signals, meaning they won't be useful for intercepting video signals once Russia figures out how to use digital signals. Still, the D·Vision SDR is claimed to have digital UAV detection, although it’s only tuned towards DJI drones for now. It’s unclear what types of radios Russian drones use, though, so the company would have to recover downed units to inspect their hardware and build appropriate countermeasures. It will also be ineffective against fiber optic drones, which are both jam- and intercept-proof as they use a physical connection to communicate with their home base.

This week on Tom's Hardware Premium, we've published in-depth interviews, roadmaps, and features that you won't want to miss. To read any of the articles we feature in this weekly roundup, you'll need to first arm yourself with a subscription.

Headlining our coverage this week is our story from Laptop expert Andrew Freedman, in his exploration of how and why Apple has chosen 2026 as the time to release an OLED — excuse me — PROLED display, with touch. After all, touch is a feature that Windows laptops have sported for well over a decade, along with OLED displays, offering unparalleled contrast ratios when compared to any other panel technology. In this feature, he explores the justifications and the likelihood of Apple slowly trickling the "brand-new" functionality to its suite of devices.

• Apple finally has a touchscreen MacBook. Why now?

Last month, Micron revealed its brand-new product roadmap, featuring new DRAM devices, 3D NAND, the use of high-NA EUV lithography tools, and much more. NAND and DRAM are both incredibly hot topics, due to the ongoing rush to build faster, more capable AI accelerators, with Micron as one of the companies benefiting from the rush in demand. We go into detail about its 1δ DRAM, which is set to be manufactured on American shores. Beyond that, the company has also demonstrated its 11th-Gen NAND, which sports over 400 layers. With the next few years of its technologies explored in unrelenting technical detail, this roadmap details exactly where Micron's upcoming projects are, and where it's going next.

• Micron details ambitious DRAM and NAND roadmap — 3D NAND, High-NA EUV, new materials, and custom silicon makes a comeback

While ASML's EUV lithography machines remain in high demand, the company's latest technology, FDX Fusion, instead relies on tried-and-true DUV. Semiconductor expert Anton Shilov sits down with GlobalFoundries VP Sudipto Bose to detail the new tech, which boasts 7nm-class performance using advanced planar transistors, with broad applications across a range of devices, including within the data center. This unredacted interview transcript explores the hows and whys behind GlobalFoundries' decision to advance its FDX Fusion technologies without going down the EUV route, as many companies are currently doing, and offers an insider look at what the company might be planning in the future.

• GlobalFoundries VP details FDX Fusion technology, sporting 7nm-class performance without the need for EUV tools — company targets 2030 for high-volume manufacturing, with planar transistors in tow

Luckily, it's not all about data centers and the technologies therein, as there are actual, new consumer PC parts that we're expecting to hit the market sometime in 2027. Of course, Intel's Nova Lake platform is abuzz with rumors over its boost clocks and big last-level cache (bLLC), which is touted as the company's answer to AMD's hugely popular X3D chips.

But a new platform means new motherboards and new chipsets to get your head around. For those brave enough to be considering a new PC upgrade in this economy, we explore everything that we currently know about Nova Lake's associated motherboards, which come alongside a brand-new socket and a suite of features up and down all budget ranges.

• Intel’s next-gen Nova Lake needs new motherboards — what we expect from Nova Point and Z990, Z970, and B960 chipsets

Marvell has signed an agreement to acquire optics company Lumentum, at a value of $115 billion. The move would combine two of the biggest players in the optical market into a single company. However, the deal would significantly impact Marvell's overall optical infrastructure portfolio, especially in the realm of in-house laser manufacturing. As companies rush to build both scale-up and scale-out domains, optics remains a huge part of the AI connectivity puzzle, as copper hits its natural limits. We explore all aspects of the proposed merger in our detailed analysis.

• Marvell to buy Lumentum in $115 billion all-stock deal — combined company to supply scale-up and scale-in optics for AI data centersv

We've previously covered how much AI is disrupting cybersecurity, and the recent PHP vulnerability is merely the latest in a string of critical issues found in commonplace pieces of software, much of which forms the foundation of the modern internet. We tear apart and examine The PHP Foundation's post-mortem of the issue, their response, and more.

• PHP vulnerability post-mortem reveals bug was known two years ago — Small team of maintainers knew of the issue before it was made public, as new PHP2Shell chained exploit ravages servers

Google's Gemini 4 Carbon AI model recently topped charts as being one of the most capable frontier AI models out there. Google has historically been a laggardly competitor in the overall AI frontier race, with much more irregular releases than the likes of Anthropic or OpenAI. We explore how Gemini 4 Carbon fares in the grand AI thunderdome, and where it might have some advantages, such as being the model least likely to hallucinate.

• Google reveals new Gemini 4 Carbon AI model, narrowly beating Claude Opus 5.5 — frontier AI model is also the least likely to hallucinate, benchmarks claim

A Pat Gelsinger-backed company, Nagare Labs, has recently showcased a new type of memory named Z2RAM. It can achieve rapid, SRAM-like speeds, with the same density benefits as DRAM. The product is still in early testing, with the latest published figures and roadmap pointing toward the device potentially becoming an alternative to High Bandwidth Flash (HBF). We explore all elements of the published design documents in our technical analysis.

• Gelsinger-backed Nagare Labs’ capacitorless Z2RAM promises SRAM speed with DRAM density — latest published cell retains data for over 300 seconds at 85°C, but further figures are projected

To read any of the articles we mention above, as well as unlock Bench, you'll need to purchase a Tom's Hardware Premium subscription. Your support goes a long way in helping us to publish deeper, more insightful articles that might not otherwise be covered.

Update 11/8/2026 1:31 PM PT: Jensen Huang has now admitted to having an affair with the alleged Chinese spy and has issued a letter of apology to his family and staff, which you can read here.

Nvidia chief Jensen Huang is the center of a new controversy as the U.S. intelligence community believes that he had a romantic relationship with a suspected Chinese spy. According to the Financial Times, Alice Huang, sometimes referred to as Huang Le, was a top executive at Singaporean firm Megaspeed and was reportedly romantically involved with the CEO of the world's largest AI chip manufacturer. Notably, Jensen is currently married to his wife of 41 years, Lori Huang. It’s unclear whether Alice Huang was recruited by the Chinese Ministry of State Security (MSS) before she joined Megaspeed or after she had already established a business relationship with Jensen, but it’s been reported that the suspected agent was apparently targeting the Nvidia head to help Chinese companies gain access to banned AI chips.

Megaspeed has been accused of smuggling $2 billion worth of AI chips into China via its subsidiary Speedmatrix, although Nvidia insists the company has no ties to China. Megaspeed sits at the center of a web of companies linked to China, and it was previously connected to a Chinese gaming company called 7Road International. It was founded in 2023 and reportedly owned by Huang Le Limited, led by Ms. Huang Le, or Alice Huang, before it was sold to Swiftdata that same year. The following year, Megaspeed used Speedmatrix to incorporate, with the subsidiary having two offices in Johor, Malaysia. The subsidiary is at the center of the smuggling allegations.

Research into Huang Le, or Alice Huang, has revealed inconsistencies. There were reports that she started her career as a TV journalist working for Hunan TV and Chinese state broadcaster China Central Television (CCTV), but an executive at the former claims to have never heard of her, while she does not have a profile under the latter. After her supposed stint in media, she moved into banking and finance as assistant to the president of HSBC’s private banking division before becoming vice president at CITIC Securities, a Chinese financial services company. It’s unclear how she became involved with Megaspeed after that, but it seems Ms. Huang built a network of companies and investors around Shanghai and Zhejiang that aggressively pushed mobile gaming companies toward AI data centers.

Questions arose about how a small company like Megaspeed could commit so much to buying Nvidia AI GPUs seemingly out of nowhere, but it certainly caught Jensen Huang's attention. After the company made its massive order, Alice Huang was spotted in a LinkedIn post hanging out for drinks with Jensen Huang and other industry executives from Gigabyte and NetThunder. She was once again seen standing behind the Nvidia chief, alongside other people, one year later as he exited a Taiwan restaurant.

Nvidia has denied the allegations, saying Jensen Huang meets with thousands of customer executives annually and that they exchange ordinary business information — not sensitive Nvidia trade secrets or national security information. China has also said that these accusations of espionage on Jensen Huang by the MSS are just “groundless smears and slanders” against Beijing.

However, foreign intelligence agencies also routinely conduct “honeypot” operations, using operatives to ensnare targets into relationships to extract data and gain insight into industry secrets. While these operations traditionally targeted politicians, members of the military, and their staff, the Lansing Institute suggests that “China is employing ‘attractive women’ posing as investors, business professionals, academics, or romantic partners to gain access to U.S. tech talent, networks, and research infrastructure.”

Nvidia CEO Jensen Huang is a man who likely attends numerous meetings, and today one more was added to his busy schedule. The U.S. Congress wants to have a closed-door chat with Huang over mounting concerns about national security. The congressmen bidding for his time say last week's report spurred the move that he may be the target of espionage by a reported Chinese asset: Megaspeed exec Alice Huang (family unrelated).

The meeting was set up by Republican House representatives John Moolenaar, Brian Mast, and Rick Crawford, respective Chairs of the House committees on China, Foreign Affairs, and Intelligence. In the House's letter on the matter, the lawmakers say the aforementioned reports "raise significant national security concerns" about China gaining access to U.S. technology and information.

The previously reported claim is that Alice Huang is a Chinese plant in Singaporean data center outfit Megaspeed, siphoning information to Beijing. The Wall Street Journal (WSJ) further claims that she was recruited by Chinese authorities due to her existing relationship with Jensen Huang.

Megaspeed reportedly bought and continues to buy billions' worth of Nvidia's chips, according to The New York Times (NYT), and stands accused by the Department of Commerce since 2024 of smuggling $2 billion worth of advanced silicon to China.

The backdrop for the situation is that the U.S. has long-standing export controls blocking Nvidia and AMD's most advanced AI accelerator chips from reaching China, among a number of other nations. The allegations were first published last week in the NYT, and are reportedly sourced from unnamed U.S. intelligence officials.

The House says the purpose of the briefing with Jensen Huang is to discuss "Nvidia's security protocols against foreign adversary espionage and [his] interactions with [...] Alice Huang." According to the NYT, the CEO never got a "defensive briefing," essentially a warning for potential targets of foreign espionage, to acquaint them with signs of such activities.

The publication notes that intelligence officials often hesitate to inform potential targets of espionage, as doing so may make the spy aware they're being investigated. The NYT adds that President Trump was briefed on the situation surrounding Megaspeed and Alice Huang a year ago, but chose not to act on it.

According to the WSJ, Singaporean authorities opened their own probe into Megaspeed, and even reportedly questioned Alice Huang directly. However, an official response from the country told the WSJ that it "does not implement unilateral export controls imposed by foreign jurisdictions," adding that while it's investigating Megaspeed, it's not targeting Alice Huang herself or inspecting her claimed ties with Jensen Huang or China.

The Singaporean does note that the country has "a zero-tolerance stance" on commercial fraud, pointing out that it's charged four companies and four individuals over such wrongdoings, and that they may face up to 20 years in prison.

Meanwhile, Taiwan is also seemingly keeping a close eye on Alice Huang, by inspecting her visits to the nation. The WSJ says that the country's authorities are probing her involvement with China and have her under physical surveillance.

As for Nvidia, the company seemingly reposted today the same comments it offered us last week, stating that "meetings with customers are part of a CEO's job; Jensen talks with thousands of customer executives every year." The firm adds that "[its] regional cloud customers receive ordinary business information — not sensitive NVIDIA trade secrets — and zero information relevant to national security."

The US federal Aviation Administration (FAA) is finally moving to retire floppy disks from its air traffic control infrastructure, with plans to replace four decades-old information systems across 435 facilities by the end of 2028. The agency announced the rollout on November 5, introducing a centralized platform that will give controllers faster access to weather reports, flight alerts and other operational information. “We’re moving away from outdated, manual processes and replacing technology that once relied on floppy disks with a modern system that allows controllers to instantly share critical flight alerts, restricted airspace schedules and pilot reports,” FAA administrator Bryan Bedford said, adding the agency wants to make critical information available more quickly across its networks.

Notably, the new Enterprise Information Display System (E-IDS) is designed to replace four legacy systems dating back to the 1980s. Rather than relying on separate information displays and manual processes, controllers will get a centralized view of operational updates, equipment problems, weather disruptions, and aviation advisories. The first five locations receiving E-IDS include Atlantic City International Airport, Nashville International Airport, Greater Rochester International Airport, and FAA data processing hubs in Atlanta and Salt Lake City, although the system could be extended to 453 sites by the end of 2028.

The upgrade comes amid mounting pressure on the FAA to modernize infrastructure that has become increasingly difficult to maintain. Last year, Congress approved $12.5 billion for air traffic control improvements, while Transportation Secretary Sean Duffy is seeking another $30 billion for additional upgrades. The agency problems extend well beyond removable storage. The FAA still relies on decades-old Company computers and replacement parts sourced from eBay. Its facilities also operate with separate systems that make information sharing more difficult, with Bedford previously saying “every facility is a silo.”

Communication failures have also exposed weaknesses in the infrastructure. Last month, the FAA sent a memo to airports warning about several recent outages caused by fiber optic cable cuts, which can trigger flight delays, diversions and, in worst cases, cancellations. One incident occurred in mid-October when a construction-related cable cut outside George Bush Intercontinental Airport disrupted data services between FAA facilities, forcing a ground stop. September also saw thousands of flights delayed or canceled across the Northeast after a circuit failure at a Philadelphia air traffic facility and in New Jersey.

That said, mission-critical infrastructure struggling to abandon obsolete systems is not entirely new. In June 2025, we covered the FAA's earlier modernization plans, which also targeted paper flight trips and computers reportedly running Windows 95. The agency has been gradually introducing electronic flight trips since the Biden era, with the transition expected to reach 49 major airports by at least 2028. So far, only 27 have made the switch. San Francisco has faced a similar challenge with its Muni Metro light rail network, with the city awarding Hitachi Rail a $212 million contract to replace its floppy-disk-based control system in 2024.

The German Navy has also been looking to replace 8-inch floppy drives used aboard its Brandenburg-class frigates. These disks are part of a data acquisition system connected to basic ship functions, including propulsion and power generation. Japan, meanwhile, finally moved the remaining government regulations requiring floppy disk submissions in June 2024, eliminating 1,034 such rules.

Eight years after GlobalFoundries abandoned the development of its 7nm FinFET technology, the company is preparing to return to 7nm-class performance, this time by going via a different route. Its FDX Fusion process, built on FD-SOI (fully depleted silicon-on-insulator) technology, promises 7nm-class performance using advanced planar transistors, with no EUV lithography necessary.

In an interview with Tom's Hardware Premium, GlobalFoundries' Sudipto Bose, vice president of the FD-SOI business unit, shared new details about its FDX Fusion technology, including its 8nm-class logic density, advanced planar transistors, manufacturing costs, and plans to begin commercial production in 2028. The company also explained how it intends to compete with conventional FinFET technologies and why it believes FD-SOI has a future beyond the 22nm-class generation. Some elements of this interview transcript have been edited for flow and clarity.

Sudipto Bose: I have been at GlobalFoundries (GF) for a little bit over six years, and I have been in the industry for 25+ years. I spent the rest of my career at Texas Instruments (TI), so it's really two jobs that I have done: TI and GF. Half and half engineering and business. I spent a lot of my business days in the automotive segment. This was what I was doing at GF when I joined, and now I have the FDX product line role.

Sudipto Bose: A little bit on the history of FDX at GF. GF has been investing in FD-SOI for a long time. It started [these efforts] before I joined. So I would say almost eight years now. And a lot of the investment thesis that drove us towards FDX Fusion is based on the traction that we have in the market today, right? We have quite a few customers who are ramping up. And I say quite a few; this is like high double-digit customers in the nineties that are ramping up right now.

Applications for FDX Fusion

Anton Shilov: What specific types of chips and devices is FDX Fusion designed for? Which application will benefit most from its capabilities?

Sudipto Bose: FDX Fusion will try to enhance the applications in which we play today. What do I mean by that? If you look at our current customers, they are designing chips, everything to do with connectivity. When I say connectivity, think of Wi-Fi, Bluetooth, cellular, satcom, all of that. So that is one class of customers.

There's another class of customers who are designing processors at the edge, so these are MCUs (microcontroller units) with some level of inference sitting inside. Think of customers like Alif Semiconductors. So that is another class: MCUs at the edge.

Then in automotive, we have a disproportionate exposure to radar, and this is because of the eighty-one gigahertz performance that FDX brings to the table. So we will engage with them as they try to enhance their portfolio. We also have an automotive MCU, but radar is where you will see a lot of press releases that we have done.

Last but not least, we also have exposure in the data center segment. This also goes back to the fT/fmax, the high-performance RF that we have, which is a good candidate for designing TIAs and clock recovery circuits.

Anton Shilov: By applications inside data centers, what exactly do you mean? CPUs?

Sudipto Bose: Not CPUs. It is in the connectivity space. So, if you think about GF's focus, we are very focused on two things in data centers: power and connectivity. So in the connectivity space, we have silicon photonics, or turning electrons into photons. But then when you receive them, you have the optical diode, again, a GF silicon photonics technology. After that, you need circuits that will amplify those weak electrical signals and drive them to the compute chip. This circuit, which amplifies the weak electrical signals, is right now being done by GF silicon-germanium, but once FDX Fusion is there, we'll offer them both [as] options. And so, to be very specific to your answer, these are data/signal paths inside the data center that feed into CPUs.

7nm-class FD-SOI node

GlobalFoundries' FDX Fusion is a new manufacturing technology that promises 8nm-class logic density and 7nm-class power and performance without EUV lithography or FinFET transistors, which greatly reduces design costs and manufacturing costs at the cost of significantly lower transistor density compared to 7nm-class nodes.

Instead, the process relies on advanced planar fully depleted silicon-on-insulator (FD-SOI) transistors, strained silicon substrates, and aggressive optical patterning techniques to achieve transistor dimensions comparable to those of conventional 8nm-class FinFET nodes.

FDX Fusion also retains support for adaptive body biasing and combines high-density digital logic with RF, analog, and embedded memory capabilities. The technology will be manufactured using deep ultraviolet (DUV) lithography, although its tighter gate and metal pitches will likely require extensive multipatterning for the most critical layers.

Anton Shilov: What are the key innovations of FDX Fusion compared to predecessors and other nodes that are currently used?

Sudipto Bose: The key things that we're improving from the current-generation FDX, the first one is fT/fmax, this is 500 GHz, or 0.5 THz fT/fmax. This helps the first segment that I talked about, which is connectivity. This helps automotive radar, and this definitely helps the data center segment as they try to improve data speeds. So this is not really competing with silicon germanium. Think of it as silicon germanium at the very high end, and FDX in the 100 – 200 Gb per lambda space. That is one. The second one is the inference at the edge. So we can call it physical AI, and we look at physical AI as sense, think, act, and connect. But the kind of feature set we are putting in starts with improving the digital gate density. This is 2.2 times more dense than the current generation FDX (22FDX and 22FDX+).

Sudipto Bose: We are putting in a lot of flavors of eNVM, a lot of flavors of SRAM, because in edge AI, and in fact for any AI, the real game is how much memory you can pack without increasing the cost. So we are adding a lot of flavors of those. The way we architected FDX Fusion is that we set a goal of how much performance we can deliver to our customer base without increasing their operating expenses.

If you look at classic 7nm, 6nm, they require EUV tools. The mask set is costly; the tool chain is costly. The FDX Fusion platform that we've built isn't going to use EUV tools. It is also based on planar technology. So there are two advantages to this. One is that we can support a much more competitive mask set price compared to 6nm. We can also offer [customers] a lot more flexibility in terms of cycle time and in how many places we manufacture, because FDX Fusion does not need EUV tools.

So, to summarize the answer? We are trying to improve RF and analog performance, digital gate density, and the classes of memory that we offer. What applications are we trying to target? It is connectivity, edge AI, high-frequency mmWave, automotive radar, and definitely applications inside data centers.

Anton Shilov: You just mentioned transistor density. The press release says that it has more than twice the transistor density of the original 22FDX process, but you never actually published a transistor density number for this. Could you share any numbers?

Sudipto Bose: I will share a number with you. But I will also give you a little bit of context on how our customers look at our technology portfolio. If you look at the current generation, the one that we are manufacturing today, the one where I said we have 90+ customers ramping. Not designing, ramping. This basically comes from the flexibility of FD-SOI. You have the box, the depleted channel, and you can use body bias. So we have customers who are able to achieve 16nm-class power and performance with 22FDX. What do I mean by 16nm-class power and performance?

It essentially means that although our gate density is not as close to 16mm, when you look at the system-level requirements like CPU clock, but think of it as TOPS per watt, we are matching 16nm; in some cases, we are matching 12nm-class.

[...] If I were sitting in a time machine and went back seven years, instead of calling it 22FDX, we could have called it 16FDX, right? Or we could have called it 16nm-class FDX. So with that analogy, if you come to FDX Fusion, our gate density of FDX Fusion will be exactly the same as the industry's 8nm standard today.

It is 14 million gates per square millimeter; that is the density.

Note: Assuming he uses a two-input NAND gate as its reference, each gate contains four transistors, which translates to 56 MTr/mm², which is comparable to what Samsung's 8nm-class nodes use.

Sudipto Bose: Now, why do we call it 7nm-class? Or we actually thought of calling it 6nm-class, but then we said, let's wait for some silicon before we go too far ahead. It is because digital gate density is one aspect of a solution. It defines your physical size, the die size, and that is great. But then you need power and performance. And with the adaptive body bias (ABB) capability that FD-SOI has, and with the standard cell metallization innovations that we have brought in FDX Fusion, once a device is done and you again look at TOPS per watt, it should be equivalent, if not better, than what 7nm can achieve. That is our product target. So for a customer, the value it brings [customers] is: 'I do not have to use an EUV tool line. I do not have to use a mask set that costs many millions of dollars.'

I have something which costs a few millions of dollars, has great cycle time, but at the same time, I am getting TOPS per watt, which is similar to or better than 7nm. The die size might be bigger, but again, it should not be no bigger than what 8nm is today. And that is the messaging to the industry; that is why we say 7nm-class instead of saying, 'Hey, this is 7nm density.' We are trying to reflect what our customers have told us. That in the edge world, in the physical AI world, the size of the die is one aspect, but if the die does not meet the power requirement of the application, then the whole system will not function. So that is the push.

Anton Shilov: That is perhaps why you actually called the technology FDX Fusion instead of using some fancy number.

Sudipto Bose: Yes, because the moment we put a number [out], people put us in a box. And we want to give customers the optionality of, 'Listen, you want to design a transimpedance amplifier using the fT/fmax that we have? That's an analog circuit. No one cares about digital gate density. Go build it.'

'You want to build a simple MCU, which is just SRAM and IOs? We have 14 million gates per square millimeter. Go build it.' 'You want to build a mixed-signal design like a single-chip radar, Wi-Fi, a satcom digital beamformer? Here are the few other knobs that you can turn to get the best PPA or the best system performance that you need.'

That is why we chose the name Fusion; we are trying to imply [that] we give you many options. It is the combination of all the good things the world needs to design the physical AI dream that we have put in front of ourselves, like the whole stack concept of 'sense, think, act, and connect'. Let us see if it sticks. I think it is a bold move for us to go against the grain of the way the foundry industry typically names its platforms, but we feel pretty strong about it.

Anton Shilov: So, you shared the gate density number, but could you maybe also share things like contacted gate pitch, metal pitch as well?

Sudipto Bose: In time. The reason I mention that is there is a little bit of IP involved. We want to get the first silicon out, engage with a few customers before we publish the CPP and the M(etal) layers. […] We are pushing the limits of patterning and coloring as well as gate oxide engineering to get the best CPP and metal pitches, which will enable this level of density of gates. That is, I would say in terms of R&D dollars just at a very high level, 50% of R&D dollars is on the transistor itself because we are doing strained substrates. There are multiple techniques we are using to improve the PFET and NFET performance. The other 50% is all on CPP and metal pitches.

Anton Shilov: So, are those contacted gate pitches and metal pitches comparable to conventional 7nm class FinFET process technologies?

Sudipto Bose: Comparable to 8nm.

Anton Shilov: When we talk about 8nm, basically speaking, there is only one company that actually produces chips using an 8nm-class technology. That is Samsung Foundry. TSMC and Intel Foundry do not have 8nm-class technologies. So I suppose that we should compare it to Samsung's 8nm node, right?

Sudipto Bose: That's a fair guess.

Anton Shilov: When it comes to power consumption improvements versus 22FDX and 22FDX+, how much lower power can we get using the new FDX Fusion node?

Sudipto Bose: It depends on the application, but I understand your question. So if you just normalize with [iso performance and iso power], I am giving you an answer with adaptive body bias included. If you consider current-generation FDX as the base point, the goal of FDX Fusion is to get 30% higher performance and 40% lower power. Again, it is really application-driven [in] how low you can go. But if you take the standard core, our goal is to get at least a 20% improvement.

Anton Shilov: What types of chips do you expect to benefit most from the FDX Fusion technology? You mentioned connectivity, edge AI, high RF, automotive radar, and connectivity applications inside data centers. What about application-specific AI accelerators, because you mentioned edge inference?

Sudipto Bose: From the STAC — sense, think, act, and connect — framework point of view, let me give you an example. Think of a humanoid, or a car — major applications that need to see. It needs to see and then infer what the environment is like. So the class of chips that do this vision processing at the edge to infer the surroundings will definitely be supported with FDX Fusion. The class of chips that will hear, do voice recognition, and, from voice recognition, draw conclusions, we definitely want to support [them]. Now, at the data center right now, as I said, our play is connectivity. Just translating optical to electrical signals.

If a customer wants to use a chiplet, which has a lot of memory, think of analog in-memory compute along with an inference engine, by all means we will support [such applications]. We will work with customers to see how we can play in that compute ecosystem in the data center. But in terms of pure focus, the first 10 customers that we are engaged with are either at the edge, or they are in the connectivity piece inside the data center.

Note: For those of our readers who are not familiar with ABB, this is a technique that dynamically adjusts a transistor's threshold voltage by changing the voltage applied to the transistor body. Forward body bias reduces threshold voltage to improve performance, while reverse body bias increases it to reduce power leakage. This enables chips to optimize performance and power consumption according to workload requirements. ABB is one of the key advantages of the FD-SOI technology.

Anton Shilov: Since you mentioned this, does FDX Fusion retain the active body biasing capabilities of its predecessors?

Sudipto Bose: It is an inseparable part of the platform, yes. We will launch this platform in a way that customers can use it.

New tools required

Anton Shilov: You also mentioned makers of wafer fab equipment. Will FDX Fusion use existing manufacturing equipment at the Dresden facility, or will it require substantial investments in new lithography, deposition, etching, and metrology tools?

Sudipto Bose: It will require new tools. Substantial is a relative term. If you see the amount of money being invested in semiconductors, the term 'substantial' has changed. We are going to get new tools, which is why we combined the FDX Fusion announcement event with the topping off of the Sprint expansion project. That's why we had all the luminaries from the German and the European government. There will be tool investment; we will be buying tools from the vendors. How much of it is going to be litho versus etching? Time will tell, but for sure we need new tools compared to what we have today.

Anton Shilov: But will you essentially need to completely re-equip the Dresden facility to use FDX Fusion? What percentage of the tools you have can be reused for FDX Fusion?

Sudipto Bose: We can get back to you on that exact answer because I do want to give you a proper answer, rather than a high-level answer. But I will tell you where the targets are. With the front end, the transistor fabrication tool chain, my target is to reuse as much as we can.

Anton Shilov: You also mentioned that you plan to begin manufacturing FDX Fusion in 2028. But does this refer to risk production, initial customer production, or high volume manufacturing?

Sudipto Bose: Initial customer production.

Anton Shilov: When do you expect the technology to reach mature yields and meaningful production volumes?

Sudipto Bose: I will give you my target, and then the industry will define it because we are a part of a bigger ecosystem. 2030 is when we want to get to high-volume manufacturing with FDX Fusion. But again, it depends on the first applications and the first few customers.

Readiness

Anton Shilov: Speaking of customers, you probably already have customers who are committed to production, haven't you?

Sudipto Bose: We have customers who are committed to building a chip. Of course, we have to deliver to their specs before they go to production.

Anton Shilov: I suppose the customers that you mentioned in the press release like BMW, Bosch NXP, Siemens, and Tesla, they are all plan to build chips on this technology.

Sudipto Bose: […] They have been pushing us for the last few years to do something like this, and they have given us requirements. Now we are doing it, and we have to show them what we can [deliver]. So there is a lot of push that we have received from the industry, from these companies. When I say these companies, the supply chain that leads into these companies to deliver something which will work at the edge. So we are racing against time to show them something that will meet the specs.

Anton Shilov: GlobalFoundries plans to release the initial FDX Fusion PDK in mid-2027. But when do you expect complete digital, analog, and RF design flows to become available from the three major EDA vendors?

Sudipto Bose: Yeah. I wish I could tell you… Right now we are in discussion with all the major primes, so we are in the request for information/request for quotation (RFI/RFQ) phase, but we have started discussions with the major EDA vendors. It has been almost six to nine months now.

Anton Shilov: But you do expect all the leading EDA vendors to support FDX Fusion in eight to nine months?

Sudipto Bose: Of course. We are going to engage with the whole ecosystem that we have, and once [the PDK is out], we have to support a proper flow not just for chip design, but also IPs that are required and everything else around it.

Anton Shilov: So how extensive will the initial FDX Fusion IP ecosystem be? Will customers have access to silicon-proven standard cell libraries, SRAM compilers, embedded non-volatile memory, interface IPs, maybe analog and radio frequency building blocks before 2028?

Sudipto Bose: Yes. In the first two years, we are going to engage with pilot customers. Think of these as early adopters. We have early adopters listed, and we will design standard cell, I/Os, and SRAM [...] needed for everything, so we will have those. But then the complex IPs, like PCIe Gen 4/5 or LPDDR6 or a DisplayPort, will be dictated by the first few applications that will ramp. FDX Fusion for us is the beginning of a journey. We have been on the journey of 22FDX for almost eight years. I envision FDX Fusion to be more than that. Even on our current platforms, we keep enhancing our IP portfolio. So I expect us to be adding IPs to FDX Fusion over the next ten years.

ARC, MIPS, and Fusion FDX

Anton Shilov: GlobalFoundries also highlighted its ARC and MIPS processor IP portfolios and RISC-V expertise as part of the FDX Fusion offering. Do you plan to develop processor cores and AI accelerators specifically optimized for FDX Fusion? IPs specifically optimized for FDX Fusion? Or will you primarily port existing IP to the new process?

Sudipto Bose: MIPS is an internal customer and a partner, and we will engage with them, and they will launch a platform for physical AI that is fine-tuned, in a combination of what they have and what FDX Fusion has. ARC and MIPS are key pieces of the strategy. Having an internal customer like that just enhances our development cycle by 5X because now they can start developing fast turns of test chips and give us feedback. We did not have this capability in the past. Now we do. Once they are ready, they will start announcing stuff.

Anton Shilov: So essentially, you will both port the existing IPs to the new node, but also MIPS will likely develop something brand new specifically for FDX Fusion.

Sudipto Bose: Yes.

Costs

Anton Shilov: How will the manufacturing complexity and cost per transistor of FDX Fusion compare to 22FDX+, your 12nm FinFET technology, and conventional 8nm FinFET technology?

Sudipto Bose: This would be the most advanced planar transistor that the world has seen, the most advanced non-EUV-based manufacturing line that the world has seen. So, I would say significantly more complex than our current 22nm-class FD-SOI line. More complex than what we have on the 12nm FinFET line. We are working with every tool vendor that you can think of as part of this program, and we have given them the challenges. It goes back to your question about our contacted gate pitch and metal pitch. So, we have had multiple workshops with them over the last few quarters, and each one of them is proposing a tool recipe that they think will get this to a nice and solid yield.

Sudipto Bose: So, I guess the answer to your question is: firstly, it is definitely complex, and secondly, we are really using the entire ecosystem available to us to come up with tool configurations that will deliver this. All of this is going to happen in Dresden. We have to be competitive, so price is always dictated by the market. Our goal is to have a running cost that is significantly better than a 7nm or a 6nm class of design (due to planar transistors and due to lack of EUV masks). After that, we will work with our customers to figure out what makes sense. But you are right, the value that we want to bring in is, 'dear customers, you do not have the same operating expenses load, meaning the cost of tape-out is less than 6nm.'

And you can do multiple tape-outs because this class of devices is not something where you can design one part and use it for 15 applications. You really need 15 devices for 15 applications. So, we definitely enable that. Then, when it comes to manufacturing cost, it is a discussion with our customers. We have various business models, but the goal is to make sure it is a win-win. At the end of the day, the lower the cost we are, the more flexibility we can provide to our customers. The non-EUV path is one of the things that was dictated by our decision that we must keep this a cost-competitive platform.

Anton Shilov: So, cost-wise you want to be competitive, but it's likely comparable to 8nm.

Sudipto Bose: I will have a better feel once we are complete with what we call our M-cycles inside the fab. But I would say my internal target is that we have to be better than that.

The future of FDX

Anton Shilov: GlobalFoundries describes upcoming technology as its 1st Generation of FDX Fusion. Does this mean that you envision subsequent generations with high transistor density and performance? Maybe you can share some preliminary targets or timelines for the next node?

Sudipto Bose: We have listed quite a few innovation steps that we want to enable on this platform. The FDX Fusion definition is based on the ones we believe we are more confident that we will be able to deliver in the timeframe that we have said. We have kept a few things in the innovation lab, and they are pushing the boundaries of a few things like eNVM, EDA routing, chip folding, 2.5D integration, which, once they mature, will define what the next version of FDX Fusion will look like. I do not have a timeline for the next version of FDX Fusion, though.

As we proceed through the development phase, I would say early 2028 to mid-2028 is when I expect to have a better view of when the next version will be launched. And this is also based on feedback we will get from customers. Because what we have right now is our first silicon, which is running in the lab, which we will show to customers. They will give us a lot of feedback. I am sure we will get a few things right, and at the same time, we will get a few things not so right. And that feedback, along with a few of the innovation topics I mentioned, will dictate what the next generation is going to look like. Stay tuned!

Anton Shilov: One of the reasons why I aksed about next-generation nodes is partly because TSMC typically shares its process technology roadmaps with new nodes well before it releases early PDKs for these nodes. Given that FDX Fusion is now GF's most advanced logic process, with capabilities comparable to 8nm-class technologies (i.e., more advanced than 22FDX or bulk 12nm FinFET), how frequently does GlobalFoundries plan to introduce new process technologies, and how far in advance will it disclose its roadmap?

Sudipto Bose: I would say, we are doing advanced development across the board. If you look at the work we are doing on silicon photonics, on packaging, on power transistors like GaN, RF GaN, Power GaN, these are all pretty advanced. But yes, you are right: in what the world understands as a classic, let's say, high-density process, FDX Fusion is the most advanced. We typically announce or update the industry about our roadmap every year at the GlobalFoundries Technology Symposium. Like this year at GTS, we announced FDX Fusion. So, I would say stay tuned for the GTS sessions that we have, and typically every year we do it in September or October.

CEA-Leti involvement

Anton Shilov: CEA-Leti describes FDX Fusion as a single-digit FD-SOI node. How closely is this new technology related to CEA-Leti's own research in 10nm and 7nm with their SOI nodes?

Sudipto Bose: The platform that we have right now is the outside of the substrate engineering work that we are doing with Soitec and CEA-Leti; the rest of it is GF inherent IP at this point in time. So we are bringing in the knowledge that we have from current-generation FDX, the knowledge that we have from the work that we did in 7nm before we stopped it, the work that we have done on 12nm. So it is bringing in all the innovations across all the GF fabs to figure out what is the best that we can offer. Does it mean that we will not look at what CEA-Leti has in the future? I do not have an answer right now. But for now, FDX Fusion is a very GF innovation-driven effort.

Anton Shilov: So you did not use pre-competitive IP from CEA-Leti to develop FDX Fusion? Is it a completely internally developed node?

Sudipto Bose: Correct.

Anton Shilov: The press release mentions innovations in substrate engineering along with endorsements from CEA-Leti and Soitec. What exactly does that involve, and how does it improve transistor performance? What role do Soitec and CEA-Leti play in developing FDX's strained silicon substrates, and how close is this technology to mass production?

Sudipto Bose: GlobalFoundries is working with CEA-Leti and Soitec under the FAMES program to develop strained silicon substrates for FDX Fusion. The goal is to improve charge carrier mobility and, consequently, transistor performance. Since FD-SOI technology relies on specialized silicon-on-insulator wafers supplied by Soitec, the three organizations are developing ways to introduce strain into these substrates and make the technology suitable for high-volume manufacturing. The approach has already demonstrated its viability in the laboratory, and the partners are now refining the manufacturing process to prepare it for commercial production.

[Session ends]

A Microsoft data center under construction in Amsterdam, the Netherlands, has been overrun by about a hundred protesters, with some carrying placards saying, “Screw your data center.” According to Reuters, the “Stop Dirty Data Centers” coalition is planning actions across 16 countries on November 6 and 7, 2026, including Amsterdam, Dublin, Warsaw, and another Microsoft site in Denmark.

Pure Data Centers, which owns the Amsterdam data center, said, “We respectfully ask those on site to leave safely and engage with us in dialogue about the development and any concerns they may have.” The report also quoted Microsoft saying that it understood the strong feeling that people have and respected their right to peaceful expression but says that it does not condone any unlawful action.

"On 6-7 November 2026 we are taking action across Europe to say Stop Dirty Data Centres," the group's website reads. "Local communities are rising up to stop dirty data centres where they live. We will unite and exercise our democratic rights to speak out, assemble, and protest to hold elected officials to account. We’re calling for an immediate moratorium on large data centres in Europe!" A map on the site shows actions planned at 85 locations across Europe over the coming days.

The group cited a list of concerns about "the explosion of AI data centres across our towns and cities," and claims to be joining to prevent "the irreparable harms data centres pose to the wellbeing of people and planet." They cite local communities, jobs, housing shortages and rising energy bills, the climate crisis, heatwaves and water shortages, big tech undermining democracies, the mental health crisis, increased surveillance and the erosion of privacy, securitization and militarization, and a toxic supply chain as motivations.

Data center opposition is one of the issues that has taken center stage in the U.S. midterm elections, with Americans overwhelmingly voting against them. It seems that resistance isn’t limited to the United States, though, as European countries take measures to limit their unlimited development. For example, Google has been hit with a criminal probe after its Finnish subsidiary, Tuike Finland Oy, allegedly destroyed 816 acres of forest without a permit. Denmark has also hit the brakes on data center grid connection requests as total applications exceed 60GW, more than eight times the country’s current peak power consumption. One Italian council also a 200% tax on data center development in agricultural land to encourage developers to reuse old industrial areas instead.

The Stop Data Center coalition claims that it isn’t against progress or that it wants to close down existing projects. Instead, it wants AI data center construction to be held until governments have established clearer rules on their development so that they do not have leave a negative impact on the environment and the people living around them. “AI, of course, is a super important ​technology and we ⁠need to have our own capacity,” EU tech chief Henna Virkkunen told the publication. But she also added that “it's very important for citizens that they can trust that their energy bills are not skyrocketing and there are not electricity blackouts because of ⁠data centers, ​or they are not destroying the environment with these projects.”

Southeast Asia computing providers are now reportedly required to register with Nvidia's Fleet Intelligence tracking system if they want to become official Nvidia Cloud Partners (NCPs). The move, according to Bloomberg, is aimed at giving the chipmaker another way to monitor where its AI accelerators are deployed, as Washington grows increasingly frustrated with restricted hardware finding its way into China through regional smuggling networks. Nvidia was not immediately available for comment.

The NCP designation is worth pursuing as it gives cloud providers Nvidia's public endorsement and preferred access to its sought-after AI chips, putting the company in a position to use those benefits as leverage. Customers seeking the status must now enroll in Fleet Intelligence, according to people familiar with the new requirements. Fleet Management was introduced last December primarily as a data centre management tool. It gathers information about NVIDIA hardware deployed across participating companies' infrastructure, including the locations of individual accelerators. That information could give Nvidia a better picture of whether its chips are operating after they leave the supply chain.

The system is, however, a universal tracking mandate. Participation has remained voluntary outside the NCP requirement, and Nvidia does not automatically receive location data from every customer using the software. The company has also not clarified whether existing Cloud Partners will have to enroll to retain their designation or whether the requirement will eventually extend beyond Southeast Asia.

Notably, Nvidia has been developing a way to locate AI for some time now. Last December, we reported that the company had developed software-based GPU tracking, using GPU telemetry and network latency measurements to estimate where processors are operating. Nvidia described the software as a customer-installed agent for monitoring hardware health, integrity and inventory.

The technology has an obvious use beyond data maintenance. The U.S. restricts Chinese companies from purchasing advanced AI accelerators without a license, yet authorities believe billions of dollars worth of the hardware have reached Chinese buyers through third-party networks, with Southeast Asia becoming an important transit point for those transactions.

A C4ADS investigation has previously identified several routes used to move restricted processors into China, including purchases through research initiatives, shell companies and shipments routed through other Southeast Asian countries. The nonprofit examined transactions between 2022 and 2025 and identified $13.4 million worth of Nvidia A100, H100, and AD102-series GPUs moving through regional trade routes. Its report also linked $4.6 billion in hardware purchases to Singapore-based Megaspeed International.

Megaspeed has become a particularly awkward case for Nvidia, with the company being under U.S. and Singaporean investigation for more than a year over suspected chip diversion. Last week, Nvidia CEO Jensen Huang defended his dealings with the firm, describing them as “completely normal,” adding, “we’ve studied all their deployments of our GPUs and counted every one.” Megaspeed denied any wrongdoing. In April, Megaspeed’s Malysisan data centre landlord terminated its contract, reallocating 68.4 megawatts of capacity to another cloud provider

Moreover, Megaspeed is not the only example of how difficult it can be to police the movement of AI hardware. Earlier this year, U.S. prosecutors accused people associated with Super Micro of helping divert around $2.5 billion worth of Nvidia-powered servers to China through Southeast Asian intermediaries. The alleged scheme involved falsified paperwork and dummy server shells, with genuine hardware shipped onward after inspections. More recently, the company has faced additional scrutiny over its export compliance after inspections. Nvidia has also reportedly removed half of the Asian companies on its pre-approved buyer list and told cloud providers to keep at least 51% of their computing services with customers outside China.

Internet and telecommunications provider Brightspeed is reportedly in talks with Nvidia to convert several of its buildings into tiny data centers. According to The Information, Nvidia pitched the idea to Apollo Global Management executives, the parent company of Brightspeed, who then asked it to submit written plans to the internet provider. Nvidia complied and has now requested additional information, data, and site visits to some of Brightspeed’s existing infrastructure.

The telecommunications company has around 130 buildings located around the country, many of which are already built to handle data and voice traffic and have the required power infrastructure to run Nvidia servers. Sources say that the AI tech giant estimates that these sites could collectively deliver around 1 gigawatt of compute capacity, which could accommodate more than 2,200 Supermicro Vera Rubin NVL72 racks containing 72 Rubin GPUs and 36 Vera CPUs each. Although these sites already can power these GPUs, it’s still not a plug-and-play solution, as Nvidia would still need to install cooling systems and other supporting architecture. These would still require permits and approval from the local government, but they would likely face less red tape and opposition compared to building a data center from the ground up.

Apollo Global Management has already made significant bets in AI hardware, with the asset management company involved in a $40 billion deal with SpaceX that would give it around 360,000 Vera Rubin GPUs across 5,000 NVL72 racks. While it’s currently unclear who will own the AI chips installed in Brightspeed facilities, the proposal could potentially help Apollo find a place for the Nvidia chips it ordered to get them up and running as soon as possible. This is a much better solution compared to waiting for years to get a data center approved, all while facing resistance from the community even after getting the go-ahead from the local government.

Having multiple small data centers like this is also a setup that OpenAI and Anthropic have been considering, especially as larger facilities are facing delays and backlash from the communities that they’re in. While having a large, homogeneous cluster built in one location is preferable for training, Nvidia representatives have described these smaller sites working together as an “inference network” to help run existing AI models. This is especially important as AI agents, which use five to ten times more tokens than humans, become more popular.

The move to use existing facilities instead of building new ones from scratch has received renewed attention, especially after Americans overwhelmingly voted against data centers during the midterm elections. While the more than 300 data center bans enacted across the U.S. have only delayed three existing projects, it’s feared that the bans and moratoriums would make it that much harder to start new data center developments and make it difficult for AI companies to secure the compute capacity needed to power their AI models in the future.

A University of Chicago law professor has warned of the dangers of using AI for mundane tasks after Claude AI accidentally deleted an entire year of Constitutional Law lecture notes and his entire current syllabus. While the files were later recovered via Dropbox, William Baude shared the story as a public service announcement, the latest story shared in a line of unfortunate AI missteps as proliferation increases.

Baude, who is the Harry Kalven, Jr. Professor of Law and the Faculty Director of the Constitutional Law Institute at the University of Chicago Law School, says he tasked Claude (it is unclear which model he was using) with updating the page numbers in an old set of lecture notes. This seemingly routine task went south quickly, however. Returning from his lunch break, Baude found a note from Claude which read, "I deleted your Fall 2026 FINAL syllabus .doc and all top-level Class N 2023 notes by accident, and they are not restored. The page check found one wrong cite... but I haven't edited the notes."

The AI then politely asked if Baude could restore the files from Dropbox, or whether it should retry from the browser pane, to which he replied, perhaps understandably, "WTF!!!!." Baude's experience is a lesson in always backing up important files, especially files you're letting AI tinker with. His plight is interesting because the AI seems to have deleted the files by accident, rather than of its own volition.

While it's still concerning that an AI model or agent could err to this degree, it's not quite as egregious as other unsupervised AI agent shenanigans we've seen in the past. In October, an AI agent reportedly deleted an entire TV show's edit weeks before release, meaning the show couldn't air. In April, a Claude agent deleted an entire company database in 9 seconds, unprompted, after coming up against a barrier and deciding the only course of action was to delete a Railway volume.

Other agents and AI models have deleted files unintentionally, such as when Claude mistakenly deleted a developer's entire profile directory (ironically, while trying to back up the files), blaming the slip-up on a typo, but often agents deleting files and directories is a case of mistaken or misplaced initiative, rather than outright negligence or error.

As is always the case, Baude's AI was extremely apologetic about the whole situation. "You're right to be angry," it confessed, "I deleted your files through my own carelessness, and you shouldn't have to clean it up."

Tesla has disclosed its revamped AI accelerator roadmap that sheds some light on the future of the company's chip development efforts. The Elon Musk company expects that its 6^th Generation inference accelerator will bring 80X more compute performance than the existing 4^th Generation chip, whereas its D3 training accelerator will cease to use SRAM-centric architecture in favor of a multi-chiplet design with stacked HBM. Also, Tesla has adopted the term "super intelligence" instead of artificial intelligence for its AI accelerators, renaming them with SI monikers. Musk recently confirmed SpaceXAI would be redubbed SpaceXSI for the same reason.

Dojo D3: No more wafer-level integration?

Perhaps the most interesting development in Tesla's AI hardware roadmap is the re-emergence of the in-house developed Dojo training accelerator after Elon Musk cancelled the whole wafer-level Dojo project in August, 2025, and then said SpaceX and xAI would exclusively use Nvidia hardware in August, 2026, both in its terrestrial and extraterrestrial data centers. Yet, the 3^rd Generation Dojo will be considerably different from the first two generations, Dojo D1 and Dojo D2.

Tesla describes its next-generation Dojo 3 (D3) training accelerator as a chiplet-based design that combines 2.5D and 3D packaging technologies with stacked HBM. This represents a substantial departure from the original Dojo D1 system-on-wafer architecture, which relied on distributed on-chip SRAM and interconnected 25 D1 processors with 11 GB of SRAM using wafer-scale packaging technology. The adoption of HBM suggests that Tesla intends to substantially increase memory capacity, as modern AI models consume extreme amounts of memory to store parameters, activations, and intermediate data, making SRAM unattractive from a capacity standpoint. The use of HBM simplifies memory scaling but introduces different latency, bandwidth, packaging, and power trade-offs. Yet, it remains unclear whether the company has abandoned wafer-scale integration altogether.

On the one hand, it is possible to stack custom HBM modules on top of logic dies interconnected using wafer-scale packaging technology. On the other hand, wafer-level integration is expensive and makes the most sense for select use cases, which include SRAM-centric architectures. Stacking HBM atop wafer-scale interconnected logic dies adds further design complexities, cooling challenges, manufacturing complexity (i.e., potentially reducing yields), long-term reliability concerns, and ultimately costs. While most of the challenges can be resolved by adding redundancy and refining process technologies, this all comes at a cost, making wafer-scaling less likely for D3.

Tesla has yet to disclose D3's compute performance, memory capacity, manufacturing process, or development schedule. At the same time, it claims that its Dojo D3 will be optimized for 'space, training, and scaling,' which means the unit will offer decent performance and will be easy to scale (which again points to a more conventional architecture of accelerators rather than to wafer-scale packaging). More intriguingly, the D3 is also set to be optimized for extraterrestrial deployments, which probably means radiation hardening for at least select SKUs.

SI6: 80X more performance than HW4 in a few years

Another interesting detail in the roadmap is the disclosure of approximate compute performance of Tesla's 6^th Generation inference accelerator (SI6): 80X compute improvement over HW4 and 9X more memory over HW4. Depending on how HW4 performance is measured (read on for explanation), we are talking about 17,280 – 46,080 TOPS (trillion operations per second), or 17.28 – 46.08 POPS (quadrillion operations per second), though we do not know anything about data formats supported by SI6. Of course, these are estimates, so take them with a grain of salt. To put the numbers into context, Nvidia's Rubin GPU offers 50 NVFP4 PFLOPS for inference, 35 NVFP4 PFLOPS for training, and 17.5 FP8/FP6 PFLOPS. Meanwhile, Rubin is shipping to customers today, whereas SI6 is due in 2029 – 2030. There are some additional details about SI6, which we will discuss below.

Tesla's existing 4^th Generation inference processor used in the company's automobiles today (which was originally called HW4, then renamed to AI4, then to SI4) is made by Samsung Foundry using its 7nm-class process technology and relies on conventional flip-chip ball grid array (FCBGA) packaging (note that the alleged Tesla slide contains a mistake and claims that the unit is made using a 5nm-class node) as well as presumably 16 GB of GDDR6 memory. The company describes the processor as the current benchmark for its Full Self-Driving (FSD) technology, which makes it the baseline against which performance of future generations is measured. Meanwhile, Tesla does not officially disclose the chip's absolute compute performance numbers, memory capacity, or power consumption, which makes comparison hard. Elon Musk once said that HW4 is 3X – 8X more powerful than HW3, which was officially rated at 72 TOPS, making HW4 a 216 – 576 TOPS ASIC (note that these are estimates).

As expected, the slide re-confirms that the upcoming 5^th Generation inference accelerator called SI5 (aka HW5 aka AI5) will be manufactured using 3nm- and 2nm-class process technologies at TSMC and Samsung Foundry, respectively, and will adopt a multi-chip module (MCM) design, marking a departure from the conventional packaging approach used for HW4. Tesla expects SI5 to deliver a 40X performance improvement over HW4, which will be a result of an eightfold increase in compute capabilities (driven by considerably denser process technologies and more execution units) and a fivefold gain from silicon optimization, according to Elon Musk, which points to 8,640 – 23,040 TOPS (an estimated figure), depending on how one counts performance of HW4. Meanwhile, the processor is expected to consume from 250W to 800W depending on application, so making performance estimates at this point is not exactly a good business. Meanwhile, the processor will also feature six times more memory than its predecessor (i.e., 96 GB). Depending on the memory type used (GDDR6 or GDDR7), the Tesla SI5 can offer memory bandwidth between 768 GB/s and 1.536 GB/s.

Moving on to the Tesla's 6^th Generation inference accelerator (SI6), which is set to further increase compute performance to 80 times that of HW4 and feature eight times more memory than the current-generation processor. This could translate to 17.28 – 46.08 POPS (quadrillion operations per second), depending on how to count HW4 performance, and 144 GB of memory, which is significant performance and amount of memory for an AI accelerator.

Tesla has already inked a deal with Samsung Foundry to make its 6^th Generation inference accelerators through 2033, and the new slide reveals that the unit will be made using a 2nm-class process technology. Given the fact that the chip is due in 2029 – 2030 and Samsung's recently updated foundry roadmap, we are probably talking about automotive-grade SF2A, performance-enhanced SF2P, or even SF2Z with backside power delivery. Meanwhile, a thing that strikes the eye with the SI6 is that Tesla does not envision the chip to be produced at Terafab using Intel's 14A fabrication process in the 2030s.

SI6 will retain the multi-chip module (MCM) approach introduced with AI5/SI5/HW5, which seems rational as it will be able to leverage experience it is going to get with its 5^th Generation inference accelerator and retain relatively reasonable packaging costs. Many automakers are considering adoption of multi-chiplet designs and HBM memory for their next-generation system-in-packages (SiPs), which will drive their costs. It remains to be seen when Tesla adopts HBM for its inference accelerators, but probably not with SI6.

A Pat Gelsinger-backed Georgia Tech spinout, Nagare Labs, says its Z2RAM can put SRAM-speed memory, at DRAM density, directly on top of AI chips. The founders’ own papers show a fast-improving cell that, tested up to 85 degrees Celsius, holds data for over 300 seconds. Gen 1 is projected to have 5x SRAM density with six stacked layers, 14x DRAM speed, and 3x less read energy than SRAM.

AI chips require a lot of bandwidth, and it has been challenging to get sufficient yields of high-bandwidth memory (HBM) to feed them. Even when manufacturers can get it, some reportedly plan to settle for fewer layers for yield reasons, and heat is another. Heat is also why Samsung’s zHBM, which stacks DRAM directly on the processor, is planned at only about four layers.

Alternatives include high-bandwidth flash, still in development, which stacks NAND like HBM and would sit beside the GPU, or SRAM stacked directly on the die, which is less dense and more expensive for the capacity, but also faster. DRAM, which is more capacious, can sit on top of the compute, but heat limits how hard the logic underneath can run.

That limit is already shaping chipmakers’ design path for stacked memory. Micron’s vHBM plans, for example, include heat-spreading structures. With HBM stacked on a logic die, and DRAM needing to be kept at or below 95 degrees Celsius, the logic’s heat output is capped at 220 W/cm², or 300 W/cm² with better thermal vias, according to a 2025 simulation by co-founder Shimeng Yu’s group. Nagare Labs says peak compute has grown 70% a year over the past three decades, against 20% for memory bandwidth.

The company describes its Z2RAM as “Two transistors and a shield. No capacitor,” where a write transistor places a charge on a storage node and the shield blocks noisy neighbors. The read transistor can sense without draining. In a gain cell like this, the read transistor’s gate capacitance holds the charge, so reads are non-destructive and the cell avoids DRAM’s write-back. Nagare aims for well under a picojoule per bit.

Nagare builds Z2RAM by depositing its layers on top of the accelerator and patterning them “together on one die,” much as 3D NAND flash scales by adding layers. There’s no interposer and no bonds between the memory layers, which is part of the secret sauce. One lithography exposure covers several layers at once, and standard 300 mm tools with DUV do the job, with no EUV required. The current roadmap is aiming at over 100 layers with “hundreds of thousands” of vertical connections.

Retaining data at higher temperatures is the challenge, and one the founders have probed repeatedly with their testing. A 2020 paper from co-founder Suman Datta’s group, on a tungsten-doped indium oxide two-transistor cell, had retention of 1 second at 25 degrees Celsius and just 300 milliseconds at 85°C. An update in 2025, which has Datta as a co-author, adds a third transistor and removes the gate overlap from its transistors, managing over 1,000 seconds at 25°C, up from 200 seconds with overlapped ones. It also simulated a GPU L2 at twice SRAM’s capacity but in the same area with 75–80% lower energy-delay-area product, a combined score that multiplies energy, delay and area.

Six months later, both founders showed a “folded asymmetric boosted” three-transistor cell that held data for over 300 seconds at 85°C, as compared to only 100 milliseconds for a conventional three-transistor design. That’s still below the roughly 95°C that Nagare says DRAM must stay under, so neither the founders’ published cells nor Z2RAM have shown retention above that line yet. The boosted cell is also “refresh-free,” which means data in the GPU’s last-level cache, profiled from AI workloads, doesn’t have time to decay before it is overwritten.

Physical space is also limited for this application, and the founders project their boosted cell at 0.0168 µm² at 7nm, compared with 0.0199 µm² for a high-density SRAM cell on TSMC’s 3nm (N3) process. A separate study from Yu’s group found that a four-tier, 256MB cache of two-transistor gain cells at 7nm could reach 5.7x the bit density of 7nm SRAM in the same area, in simulation. However, the return on investment falls off past seven or eight tiers because masks scale with layers. Nagare Labs’ claim of single lithography would potentially bypass this limitation.

That has not yet been proven, and nothing published yet shows it. “Where we are is literally lab prototypes,” Datta told The Register, adding that sampling of Z2RAM tiles is targeted within four years and production shipments, if they arrive, within the next decade. Yu told the outlet that no standard yet exists for integrating this kind of memory with an accelerator, which means Nagare might have to come up with the interface itself. Datta also mentioned reliability to the outlet, as single-electron effects can shift a cell’s threshold enough to upset the stored bit. It also remains to be seen if the tested three-transistor cells work sufficiently well as a two-transistor, single-shield product.

Even if Nagare clears those hurdles, a more important one lingers: It currently has no fab. The plan to scale depends on getting partners for fabrication as well as packaging. Nagare is reportedly looking for an R&D fab partner so it can scale beyond the university clean room. Perhaps the most similar type of memory-on-compute shipping today, and the one Datta cited to the outlet as a model for working with chipmakers, is AMD’s 3D V-Cache.

Z2RAM isn’t the first capacitorless memory to promise a 5x improvement over SRAM in density; it follows in the footsteps of Innovative Silicon’s Z-RAM from 20 years ago, a technology AMD licensed, though it was not pursued. A Georgia Tech paper due at IEDM in December covers a different device, a one-transistor, one-ferroelectric-transistor cell, aimed at the same gap between SRAM latency and DRAM density.

Gelsinger, previously CEO of Intel, which started as a memory company, phased out Optane, a low-latency non-volatile memory, in favor of CXL. Optane sought to bridge the gap between slower non-volatile storage, such as HDDs and standard SSDs, and DRAM. Now he sits on Nagare’s board, and Playground Global, where he is a general partner, led the startup’s $5 million round as Nagare searches for a solution to a different but related problem.

Nagare declined to share measured retention, latency, or energy figures. The founders’ boosted cell already holds data at 85°C longer than a cache needs, but until a fab-built, multi-layer Z2RAM stack is measured, retention above 95°C included, its headline numbers remain projections.

The internet is still reeling from the PHP engine vulnerability and all other security vulnerabilities found over the past few weeks, and we're not done. Today's special is quite spicy: you can get into Alpine, OpenWRT, and other Linux distros without needing a password, thanks to a combined bug with OpenSSH and musl libc. Just randomly type over 256 characters on the password prompt and you'll be let in through the SSHhole.

It works if you set an empty password for system users, which is the default on multiple distros. The bug is present, though not necessarily enabled, across Buildroot, Yocto, and Void Linux. OpenWRT uses Dropbear for authentication by default, but users can install OpenSSH instead.

The largest concern is by far Alpine, though, as it's pretty much the default choice for what could amount to millions of installs across Docker/Kubernetes/Proxmox containers and endless dependencies thereof, servers, cloud VMs, and embedded devices, among many others. Alpine comes with the requisite conditions set and password authentication enabled by default, which is why it needs immediate patching.

Broadly speaking, the vulnerability combination is: OpenSSH, musl, password authentication not explicitly disabled, not using PAM, and the one arbitrary user with a password set, using a SHA-512/256 hash.

Patch your systems immediately, as per the project's advisory note. Meanwhile, the easiest mitigation is explicitly setting "PasswordAuthentication" to "no" in your OpenSSH configuration file and restarting the service.

While in practice the vast majority of Alpine and similar installs aren't reachable from the internet, any attacker inside a network, including but not limited to corporate setups, home labs, cloud networks, and VPNs, can let themselves in. Likewise, all it takes is one valid user account, not too hard to get in a large enough corporate environment, and then an attacker is inside the network. Scanning and testing the vulnerability is also trivial.

OpenSSH has already published a fix and an advisory post, as did musl author Rich Felker. Both parties seem to believe the other is at fault, but looking from the outside, blame is shared.

If you've ever looked in the /etc/passwd or /etc/shadow files, you may have noticed a single asterisk as a placeholder for the password hash for accounts with no password — meaning "no password should work." The SSHhole website has all the details, but the snafu happens both when musl's crypt() function returns "*" as an error condition instead of a null value as per usual conventions, and then OpenSSH uses it to compare to a password hash, when it shouldn't. An overly long input then triggers the chain of mistakes.

India wants to develop its own graphics processing unit (GPU) within the next two years as the country steps up efforts to build a domestic semiconductor industry and reduce its dependence on foreign chip suppliers, reports ETGovernment. The target was outlined by S.Krishnan, secretary of India's Ministry of Electronics and Information Technology (MeitY), in a November 4 interview. "Under India Semiconductor Mission 2.0, we intend to target the development of an indigenous GPU chip. We should have a GPU chip of our own. This will not happen overnight. It is a project that will require approximately 24 months, and we intend to work towards that objective," Krishnan said.

The proposed GPU is part of a wider plan to establish an Indian hardware and software ecosystem, with Krishnan describing five layers needed to support AI development. These include: energy, accelerator chips, computing infrastructure and servers, AI models and applications. Indian companies such as VVDN, Kaynes and Avalon are already manufacturing servers, while the Centre for Development of Advanced Computing (C-DAC) has developed its Rudra server range, whose systems are designed to support AI workloads, after which the government transfers the technology to local manufacturers. Krishnan also sees AI as a potential repeat of the opportunity India's IT industry experienced during the Y2K (the year 2000 bug) transition. "AI could create a similar opportunity, although the nature of the work will be different," he said.

The comparison is big for a country whose IT-enabled service sector employs about 6 million people. A NITI Aayog paper estimates that roughly two million existing jobs could become redundant as AI adoption changes the industry, but around 4 million more jobs could emerge. Krishnan argues that Indian companies could benefit from helping businesses worldwide integrate into their AI operations, just as they benefited from the demand for software services around the turn of the century.

The country has already attracted major interest with ASML, partnering with Tata Electronics to equip India's first commercial semiconductor fabrication facility in Dholera, Gujarat. The planned facility is expected to use 300mm wafers and eventually reach a capacity of 50,000 wafers per month. Intel also announced a strategic partnership with Tata Group covering semiconductor manufacturing and packaging for the Indian market. However, the proposed GPU remains an early-stage target. Krishnan did not identify a manufacturer, chip supplier, or builder for the project. India is also looking to bring its own homegrown SHAKTI and VEGA processors to commercial markets. Both are based on the open-source RISC-V architecture, allowing local developers to build processors without relying on proprietary CPU designs. Notably, these are CPU designs, separate from the GPUs now being targeted by MeitY.

That said, it is not the first time India has attempted to build its own GPU production unit. In 2019, India's IT Madras released a software development kit that allowed developers to begin building applications before the processors were commercialized. The project included several processor classes aimed at different markets, from embedded devices and micro-controllers to workstations and server workloads. The effort has continued since then, with the Aries 3.0 development board, which uses the C-DAC’s VEGA ET301 processor, being introduced in 2024. The 32-bit chip runs up to 100MHz and includes 26KB of SRAM and is intended for relatively simple applications such as sensors, wearables, and Internet of Things devices, rather than desktop PCs or graphics-intensive workloads.

However, there are signs that the SHAKTI and VEGA platforms are nodding beyond development boards and into practical applications. At the September 26 SEMICOM India event, the government highlighted projects using the processors, including an autonomous water-cleaning robot around SHAKTI and a digital telescope using VEGA. Another VEGA-based project was designed to monitor forest environments. The government's Design -linked Incentive (DLI) program is already supporting more of that work. MeiyT says 24 companies received assistance under the scheme, and subsequently raised venture capital or other private investment. Their projects include microcontrollers, drone flight controllers, smart meter chips and CCTV cameras.

India's semiconductor market is currently valued at just about $50billion and is expected to approach 100 billion by 2030, according to a report by the India Electronics and Semiconductor Association (IESA). The government wants local companies to capture more of that growth domestically rather than remain dependent on imported components.