Unless you already have a kit of DDR5, or deep pockets for PC hardware, you’re stuck right now. Despite seeing some of the best CPUs for gaming released just in the past year, the DDR5 tax represents a major hurdle to building or upgrading your PC. Intel’s LGA 1700 CPUs hold an unintended solution, offering support for both DDR4 and DDR5. We wanted to see if this on-ramp to a next-gen platform was really as smooth as it looks at first glance.

The idea is simple. If you already have a DDR4 kit, you can upgrade to a relatively new CPU while keeping the door open for a transition to DDR5 without buying a new chip. It’s inexpensive, and a bit more of a practical solution than upgrading to DDR5 with a single DIMM and worrying about pairing it with another later.

Our testing shows how much of a performance difference there is with DDR4 in games. We’re focused on games here for a few reasons. First, in non-gaming applications, memory speed is highly dependent on the specific workload you’re running. Games, despite using different engines, are largely similar workloads that stress the hardware in similar ways. Further, those workloads are continually evolving as new games, new technologies, and new hardware targets are released.

We kept our testing focused on Intel’s LGA 1700 CPUs because they’re the only options that give us a true apples-to-apples comparison between DDR4 and DDR5. We don’t have any AMD CPUs in our test pool because there aren’t any chips that support both DDR4 and DDR5. This isn’t intended to be a competitive analysis between AMD and Intel. That conversation opens up a much broader conversation about total platform cost.

Testing DDR4 vs. DDR5 on Intel’s LGA 1700 CPUs

To test DDR4 and DDR5’s gaming performance, we ran Intel’s main LGA 1700 stack through a 15-game gauntlet of benchmarks. Notably, we don’t have results for the Core i9-12900K, as our sample has a janky memory controller that won’t boot on DDR5 systems. You can read a full breakdown of how (and why) we tested in the way we did in the section below.

We ran all of the games through our 16-game benchmark suite, though we cut Doom: The Dark Ages from the results here. An update for the game rolled out mid-way through testing and skewed our results, so we’re omitting it. The 15 remaining games still paint a clear picture of the performance difference between DDR4 and DDR5.

As usual, we tested with the RTX 5090 Founder’s Edition at 1080p with a mixture of High and Ultra settings. We test at 1080p to maximize the differences between CPUs, and it remains the most widely-used resolution for gaming. Deltas between CPUs will decrease as the resolution climbs and the GPU becomes a larger influence in performance.

Below is our geomean from testing across the suite. Given that we’re looking to compare a single CPU’s performance with DDR4 and DDR5, we’ve highlighted some CPUs with the same color (13700K is always dark red, for instance, while 14700K is always dark blue).

The chart above is a bit difficult to parse, mainly because we’re often jumping several entries to get to a comparison point. For the stack of chips we tested, here’s a clearer overview of the performance difference with DDR4:

As we’ll get into with the individual game tests below, the drop in performance between DDR4 and DDR5 can be much larger than the comparison in our geomean (and, in turn, smaller in other games). What’s important for the overall performance drop is the trend as we move to newer chips. You can see a 9% drop grow to 14%, as DDR4 becomes a more significant bottleneck when the processor it’s feeding becomes more powerful.

That trend is one of the main driving forces behind our look at DDR4 and DDR5 gaming performance today. We looked at DDR4 and DDR5 performance extensively near the Alder Lake launch, and even more recently last year, evaluating performance across a wide range of applications. The testing here is focused solely on gaming to answer a critical question of building a PC today: Are you really giving up that much gaming performance with DDR4?

The answer is, yes, you’re giving up around 11% to 14% of your gaming performance overall when the memory is the only variable that changes. That’s a consistent drop, as well. Older titles care see less of a benefit from DDR5 generally, but we saw a steady decrease of around 11-14% across the games we tested, with some titles pushing above a 20% drop.

007 First Light is the newest game we tested, and it outpaces our averages. The 14900K sees a 16.5% drop with DDR4, while the 13600K drops 12.7% of its performance. Especially among the most powerful CPUs here, you can see DDR4 level off performance in a way that’s undesirable. The 14900K, for instance, is just 1.7% faster than the 13900K with DDR4, but it’s 4.6% faster with DDR5.

Similarly, in Crimson Desert, you can see the 13700K lose 13.7% of its performance with DDR4, and the 14600K drop 13.2% of its performance. It’s worth noting that neither of these games are particularly sensitive to memory speed. You can see in our recent Ryzen 7 5800X3D re-review that even a boost from 3D V-Cache doesn’t give CPUs with a robust memory chain an automatic advantage.

Perhaps the most consequential of the newer games we tested is Marvel Rivals, not only because it shows a much larger gap between DDR4 and DDR5, but also because it’s the most-played game in our test suite by a long shot (short of Counter-Strike 2). For weaker chips like the 12600K, the gap is 13.9%, just slightly above our geomean. For the more powerful 14700K, however, it shows a gap of 25.3%. Even the 14600K drops 17.4% of its performance with DDR4.

Counter-Strike 2 is less extreme, perhaps as a consequence of having such a high floor for average frame rates. You can see that the Alder Lake chips don’t care much about DDR4, with the Core i7-12700K performing identically across both memory standards. That gap grows with more powerful CPUs, however, with the 14700K creeping up toward a 10% delta.

In Spider-Man 2, we can see more consistent drops across the stack of chips we tested, with most CPUs dropping around 18% of their average performance with DDR4. That’s true even on the weaker 12700K, which lost 15% of its performance. The 14900K, meanwhile, was 18.7% slower with DDR4.

Even in an older, GPU-heavy title like Cyberpunk 2077, we can see a consistent drop. You can see in this game that we become completely bound by the GPU at the top of the rankings, but that’s a level these chips can’t hit when paired with DDR4. The 14700K drops about 14% of its performance, and the 13600K, about 13% of its performance.

You can browse through our remaining benchmarks using the gallery above, but most games tell a similar story. The gap between DDR4 and DDR5 persists, of course, but there’s another angle to look at the data. DDR4 flattens off performance, creating a bottleneck with faster CPUs. That could be justification for buying a weaker chip if you can only afford DDR4 memory right now.

Outside of performance, one important aspect of using a DDR4 system compared to DDR5 is power consumption. With DDR4, power consumption of the CPU increases, as you can see in the chart above. The jump is generally only a few watts, but it’s worth noting nonetheless. In games, we’re well below the operating temperature of all the chips in our test pool, but when pushing toward maximum power draw, DDR4 will post yet another limitation.

How (and why) we tested DDR4 vs. DDR5 now

DDR5 is way too expensive, and Intel’s LGA 1700 CPUs represent a unique value proposition given the unprecedented increases in memory prices over the past several months. The idea is that you can upgrade to a newer platform while sticking with DDR4, giving you a stopgap for an eventual DDR5 upgrade. It seems Intel recognizes this value proposition, as well, as it’s reportedly slated to launch Raptor Lake Next CPUs on the LGA 1700 socket.

We tested the main stack of chips, short of the Core i9-12900K, as described above. We didn’t test variants like KS releases to keep our testing focused, as well as lower-end SKUs like the 12100F or 14400. The memory controllers in these lower-end chips are weaker, sustaining lower DDR5 speeds, so expect less of a difference in performance with them.

Below, you can see the test benches we used. In addition to keeping hardware consistent, we use a frozen OS image with an identical software stack. We’re running the same version of the same apps on the same OS update, with identical drivers.

In the BIOS, we enabled XMP for both kits of memory. We also tested with Resizeable BAR turned on, and Virtualization-Based Security (VBS) turned off. Most motherboard vendors off a profile with the power limits removed on Intel CPUs, which can push the processor outside of warrantied specifications. We stuck with the default “Performance” profile for our testing here.

Is DDR4 still worth it?

It makes sense that we’ve seen a shift back toward DDR4. Although DDR4 prices have risen in lockstep with DDR5 prices, they started from a much lower base. A kit of DDR4 today is not much more expensive than a DDR5 kit of similar capacity a year ago. And, with estimates that the memory shortage could persist through 2030, there’s a strong argument for going with a DDR4 system if you’re in need of an upgrade.

The performance trade-off alone isn’t as big of a problem as it appears at first glance. You’re going to lose about 15% of your average gaming performance with Intel’s LGA 1700 CPUs (particularly Raptor Lake chips). You’ll spend more than twice as much on a 32GB kit of DDR5-6000 as you will on a 32GB kit of DDR4-3200, as you can see in our RAM price tracker. And, you might already have a DDR4 kit, cutting that cost completely out of an upgrade. Dollars spent for performance gained, DDR4 makes complete sense.

However, performance isn’t the only factor at play, and that’s the unfortunate reality of using a DDR4 platform right now. It’s a dead end, both for performance and upgrade potential. As we saw in our recent testing of the Ryzen 7 5800X3D, there’s a performance wall in games with DDR4, one which the 5800X3D often runs up against. The memory is a bottleneck, and it doesn’t seem like there’s a way around that problem without upgrading to DDR5.

We also aren’t seeing any new DDR4 CPUs, at least right now. AMD re-released the Ryzen 7 5800X3D, and there are murmurs of Raptor Lake Next. But given the current landscape, we don’t expect a CPU that will radically change the performance you can get out of a DDR4 platform.

Instead of sticking with DDR4 for a better CPU, the best course of action right now is to bite the bullet on DDR5 and buy a weaker CPU, particularly if gaming performance is your main concern. Given that memory prices are out of control, there are excellent deals on DDR5 CPUs right now, allowing you to offset the cost of an upgrade and giving you a kit of DDR5 to carry forward in future builds.

As an example, AMD’s recently-released Ryzen 7 7700X3D is $80 cheaper than the re-released Ryzen 7 5800X3D, despite coming in nearly 20% faster in average gaming performance. The $230 Ryzen 5 7600X3D shows similar gains, and it’s even more affordable.

In Intel’s camp, the Core Ultra 7 270K Plus and Core Ultra 5 250K Plus represent some of the best all-around value in the CPU world right now, with compelling gaming performance and chart-topping application performance, all for around $300.

You will spend more on a cheaper CPU and a kit of DDR5. There’s no indication that the memory shortage is ending soon, however. We’ve actually seen prices continue to increase despite the surge leveling off. Opting for DDR5 today buys you better gaming performance, but more importantly, it gives you a kit of memory that you can continue to use as new CPUs and platforms are released.

One of the common misconceptions in today's memory market is that once memory modules based on chips from CXMT enter the consumer market, there will be cheaper alternatives to memory sticks running DRAM from the Big Three. While availability of CXMT-powered modules certainly impacts average selling prices, these products are not cheaper than those based on ICs from Micron, Samsung, and SK hynix even in China, as noticed by @harukaze5719.

A 64GB DDR5-5600 RDIMM based on memory from Samsung or SK hynix costs 18,595 CNY ($2,745) at JD.com, whereas a module featuring the same capacity and specification, but using DRAMs from CXMT is priced at 18,999 CNY ($2,805), according to observations by @harukaze5719. It is noteworthy that a Samsung 64GB DDR5-5600 RDIMM made by Samsung and sold by Samsung costs $2,425 at Amazon.com in the U.S.

While the $60 difference seems significant, it is really just 2.2%, which can be considered negligible at these sky-high prices. Nonetheless, many expect CXMT-based memory modules to be cheaper than those carrying chips from Micron, Samsung, or SK hynix, so observing that they are even a bit more expensive than offerings with ICs from renowned manufacturers may be a bit surprising.

Indeed, because CXMT produces memory chips using an outdated fabrication technology, its DRAM ICs consume more power than those made using the latest manufacturing processes, have lower performance potential, and mediocre overclockability. Furthermore, the Chinese government heavily subsidizes both ChangXin Memory Technologies and Yangtze Memory Technologies (YMTC), which enables both to sell their memory at lower prices although their actual costs may be higher compared to those of the Big Three.

As a result, it is reasonable to expect CXMT to charge less for its chips compared to chips from renowned producers. Truth to be told, we do not know CXMT's quotes, they may be as high as those from other manufacturers and the only reason why module producers buy them is that they are the only chips available. Furthermore, companies tend to price products based on what the market will bear, not strictly on production cost or their characteristics. In fact, as everyone is capacity constrained these days, there is little incentive for CXMT to price its DRAMs significantly below those from renowned makers. However, while CXMT may indeed charge less for chips (e.g., because the Chinese government issues an appropriate directive), this lowers costs for module makers, but has a limited effect on retail prices of actual DIMMs or RDIMMs.

Whether potential savings reach end customers depends on market competition, supply-demand conditions, and the pricing strategies of module makers, distributors, and retailers. Furthermore, when prominent companies like Apple, Dell, or Corsair use a memory chip SKU, this one must pass rigorous validation processes and is usually tested in-house, or by contract manufacturers, which adds to costs and somewhat erases the price difference between suppliers.

As a result, CXMT memory chips may make the lives of hardware makers easier, but are not expected to impact the retail prices you pay.

You're probably already well aware of the three largest memory vendors: South Korea's SK hynix and Samsung, and the United States' Micron. There's a fourth player up and coming in the market, though, and that's China's ChangXin Memory Technologies, more commonly known as CXMT. CXMT is pumping out RAM as fast as it can to soften the effects of the RAMpocalypse on domestic (to China) consumers, and it's also expanding capacity quickly. Given these factors and the size of the Chinese market, it should come as no surprise that motherboard vendors, including Gigabyte, are advertising fresh support for the chip.

MSI appears to have been the first major motherboard vendor to publicly promote BIOS optimizations specifically for CXMT DDR5 memory, initially through China-market BIOS releases and later with global announcements. What Gigabyte is saying is a little different: not only is CXMT RAM supported on Gigabyte motherboards for both AMD's Socket AM5 and Intel's LGA 1851, but it's supported at impressive speeds of up to 8200 MT/s on select boards.

As proof, Gigabyte offers up a CPU-Z screenshot showing a pair of 16GB Lexar modules equipped with CXMT chips achieving a speed of 8200 MT/s with a CAS latency of just 40 cycles on one of its B850M FORCE motherboards. We have to remark that Gigabyte doesn't show the voltage required to hit these speeds, likely for good reason, but the firm did it without disabling the chip's integrated graphics. That doesn't prevent the chips from posting an excellent AIDA64 latency of just 65.4 nanoseconds on the monolithic Ryzen 5 8600G used for the test. For context, typical EXPO kits usually run around 80ns, JEDEC timings are more like 100ns, and LPDDR-based systems rarely come below 110-120ns.

As Gigabyte says, "CXSH (CXMT) chip-based memory offers a welcome additional source of supply for consumers." (CXSH is the JEDEC manufacturer ID code for CXMT) Gigabyte specifically notes that it is modules with 16-gigabit and 24-gigabit ICs that are supported; that means 16GB and 24GB single-rank modules, or 32GB and 48GB dual-rank modules.

While CXMT memory is certainly a welcome additional source of supply, it's also not really clear how much of that memory is actually making its way outside of China, particularly to the US and Europe. CXMT isn't on the US Commerce Department's "Entity List" yet, so the firm's parts aren't actually banned, but the company is once again considered a Chinese military company by the Department of Defense after being briefly removed from the 1260H list in February. Lawmakers here in the states, likely laden with donations from the big three memory firms, want to see CXMT banned, while US tech companies like Corsair, HP, and Dell are already integrating ChangXin RAM into their products, and Apple wants in, too.

The reality is that, as a DIY builder, you are fairly unlikely to know or care if your memory is manufactured by CXMT. You don't usually buy RAM directly from SK hynix, Samsung, or Micron (certainly not since Micron unceremoniously executed Crucial); you buy your RAM from Silicon Power, G.SKILL, Patriot, Corsair, or one of the many other vendors who assemble DIMMs. If the RAM runs at its rated specifications, there's not a lot of reason for the individual consumer to care where it came from. It's nice to hear that the new chips are officially supported by familiar mainboards, though.

As Apple and other American companies seek to use memory chips from China-based CXMT and YMTC amid massive supply constraints, U.S. lawmakers want to ban exports of Chinese memory chips to the U.S., citing concerns of weakening domestic and allied suppliers and indirectly supporting the development of 3D NAND and DRAM by Chinese companies, reports the Financial Times.

John Moolenaar, Republican chair of the U.S. House China Committee, and Democratic Congressman George Whitesides asked Commerce Secretary Howard Lutnick to prevent U.S. companies from purchasing semiconductors from businesses included either on the Pentagon's Chinese Military Companies blacklist or the Commerce Department's Entity List. They also called on the administration to add CXMT to the Entity List and impose additional restrictions on YMTC.

"Dependence on Chinese memory manufacturers creates an unacceptable risk for U.S. national security, economic security, and supply chain security," the letter by Moolenaar and Whitesides reads.

Apple has been seeking approval from the Trump administration to source memory from CXMT amid a severe global DRAM supply crisis caused by the rapid expansion of AI infrastructure. Corsair, Patriot Memory, and some other suppliers of branded memory modules and SSDs have been using DRAM from CXMT and 3D NAND from Yangtze Memory for some time now.

"We are alarmed that Apple and other U.S. tech companies seek to purchase memory from Chinese semiconductor manufacturers, including those with ties to the Chinese military," the U.S. lawmakers wrote.

DRAM maker CXMT is already on the Pentagon's Chinese Military Companies list, whereas 3D NAND producer YMTC is already in the DoC's Entity List. Their presence in the lists does not outright prevent American companies like Apple from buying their products, but at a significant political risk.

Technically, American companies could buy chips from CXMT and YMTC to use inside products bound for China or other countries and continue to use memory from traditional suppliers in products aimed at the U.S. market. To prevent this, Moolenaar and Whitesides also urge the American government to coordinate with Japan, South Korea, and the EU to prevent CXMT and YMTC from taking advantage of the current supply shortage to establish themselves in allied supply chains, which they believe could ultimately leave the West strategically dependent on Chinese memory.

Moolenaar and Whitesides argue that purchases from Chinese memory manufacturers could indirectly support technologies applicable to China's military.

"Leading Chinese memory manufacturers are all closely intertwined with the Chinese military; thus, every memory purchase by a U.S. company will directly subsidize the People’s Liberation Army's development of this critical dual-use technology," the letter stresses.

The lawmakers argue that CXMT and YMTC could repeat China’s playbook in solar, steel, telecom, and EV markets: use state subsidies to undercut foreign rivals, weaken their investments, and ultimately exploit the resulting dependence for strategic leverage. That said, using Chinese memory now could permanently weaken Western production capacity and leave the West strategically dependent on China for a critical component of AI infrastructure, Moolenaar and Whitesides believe.

Homegrown DDR5 memory from China, manufactured by ChangXing Memory Technologies, has been making the rounds lately as more and more vendors start legitimizing it. However, new testing from overclocker Safedisk, shared by Uniko's Hardware, purportedly shows that it actually carries inferior performance compared to similar options from SK Hynix, alongside significant variance in the silicon between different batches.

CXMT began producing DDR5 in late 2025 despite lacking any cutting-edge EUV lithography tools. Fast forward to today, and reports of the company matching Micron's memory capacity by this year are now floating around. If true, China would become the second-largest memory maker in the world. At such scale, it's no wonder that many companies in China have already started sourcing CXMT-made RAM to fill the gap in the consumer market.

Throughout 2026, we've seen motherboard manufacturers verify CXMT's DDR5 with official BIOS optimizations that allow it to run beyond 8,000 MT/s at this point. OEMs such as Dell and HP are using CXMT RAM in their region-bound systems, and even proper PC hardware companies like Corsair are using CXMT modules. Lexar, Kingbank, Netac, Asgard, Gloaway and more are also producing retail DDR5 kits with CXMT chips.

As such, the testing features a Kingbank 48GB (2x24) DDR5-6000 kit running at CL36 and found several weaknesses despite successfully achieving an 8,600 MT/s overclock at CL44. The first revelation is that CXMT modules don't scale with voltage, meaning you can't just increase voltage in hopes of achieving higher clocks. CXMT's DDR5 apparently doesn't respond well to tuning sub-timings either, forcing you to remain stuck with baseline CAS latency (or higher, like in this case).

Different batches of CXMT-equipped memory perform differently, too, so silicon lottery plays a much bigger role than it would with other vendors. Speaking of which, SK Hynix-made DDR5 modules allegedly performed better at identical clock speeds, while CXMT's modules were less susceptible to overclocking in general. We didn't get any comparative benchmarks for any metric, so take these claims with a grain of salt.

Overall, if the testing is to be believed, it serves as counterprogramming against the popular narrative forming around China as the savior of consumer interests. CXMT's strength lies in the fact that it doesn't have to cater to opulent AI clients as much as the Big Three, which reduces opportunity cost, allowing CXMT to produce more DDR5 memory. That doesn't mean it would be cheaper, though, or at least no evidence has suggested that so far.

CXMT has remained limited to the Chinese region for now, and breaking through to the Western market would mean impressing a lot of skeptics. Not only would pricing play a big factor, but the reliability of a new DRAM manufacturer would raise serious concerns. Stories like these certainly don't help, but with CXMT's IPO on the way, it's only a matter of time before it becomes a serious mainstream contender.

ChangXin Memory Technologies (CXMT), China's largest DRAM maker, is on track to match Micron's production capacity in 2026, if Citrini Research's forecasting models are correct. If this happens, China will become the world's second-largest DRAM production base in the coming years.

The bottom-up model estimates that CXMT will finish 2026 with approximately 350,000 wafer starts per month (WSPM) of DRAM capacity, which is just 25,000 WPM less than Micron. According to the analysis, the federal government is pushing CXMT to share its DRAM technology with JHICC, Swaysure, and YMTC's subsidiary XMC to ease domestic shortages. All three companies have either built DRAM capacity already, or will do so in the short-term future, the report claims.

Swaysure has completed construction of a 140,000-WSPM fab in Shenzhen, while JHICC's Jinjiang complex contains enough cleanroom space for 120,000 WSPM, and the initial 60,000-WSPM phase is expected to receive equipment by the end of 2026. YMTC is also projected to operate about 50,000 WSPM of DRAM production at Wuhan Fab 3. If all these facilities initiate operations in the coming years, then China will have a total DRAM capacity of 600,000 WSPM (not counting Samsung's and SK hynix's fabs in China), which is dramatically lower compared to South Korea, but ahead of Japan, Taiwan, and the U.S. combined.

But China is not going to stop developing its DRAM industry, and by 2030, its total capacity will increase to around 1.41 million WSPM, according to Citrini. CXMT alone is projected to build new production capacities in Beijing, Hefei, and Shanghai, to expand its production capability to 950,000 WSPM in 2030, assuming everything goes as planned.

The supply model assumes that about 400,000 WSPM of CXMT output will remain on D1a, another 400,000 WSPM will migrate to D1b, and roughly 150,000 WPM will produce D1c devices.

Enough fab tools?

Citrini admits that producing China's outlook is considerably more difficult than predicting the development of established DRAM makers. On the one hand, there is rapidly expanding fabrication infrastructure in China, abundant state-backed financing, and government-directed technology transfers. On the other hand, among the key near-term limitations remains lithography equipment availability, particularly if the proposed MATCH Act restricts sales of advanced immersion DUV tools to select Chinese companies.

However, the author expects SMEE's domestic immersion DUV scanners to enter volume production around late 2026 or early 2027 following beta testing, as well as SiCarrier/Yuliangsheng introduce its own production-ready DUV platform in 2028. Perhaps a bit optimistically, the analysts predict that availability of lithography tools is not expected to constrain Chinese production beyond 2028, at least for mature logic and DRAM nodes. Yet, for obvious reasons, if the MATCH Act works as planned and disrupts supply of advanced immersion DUV tools to DRAM makers, production capacity expansions will not occur in the next couple of years, the report suggests.

Still, both SMEE and SiCarrier will need time to ramp up production of their lithography systems, whereas DRAM makers must learn how to use them efficiently, so we would not be as optimistic as the authors and would not expect Chinese tools to produce meaningful DRAM volumes before the early 2030s. Still, the key takeaway here is that China is on track to become a major DRAM maker rather sooner than later.

Unprecedented demand

Citrini Research projects total DRAM demand to reach 157.5 exabytes (EB) per year by 2030, including 75 EB of commodity DRAM for agentic AI CPUs, 25 EB of commodity DRAM for conventional cloud servers, 20 EB of commodity DRAM for client devices, and 37.5 EB of HBM4E as well as HBM5 for AI accelerators (15 EB and 22.5 EB, respectively).

Meanwhile, Citrini expects the whole industry to only produce around 37.5 EB of HBM4E/HBM4 memory (mostly by Micron, Samsung, and SK hynix) as well as 91.3 EB of commodity DRAM (including output in China) in 2030, leaving a deficit of 28.7 EB, or roughly 25%.

That said, the rapid expansion of DRAM production in China could be the industry's best hope to maintain relatively low prices of memory, something that will be particularly beneficial for the market of consumer devices that are sensitive to memory prices, analysts from Citrini believe. Yet, the author argues that most of this new capacity would satisfy China's own demand rather than eliminate the global shortage. Furthermore, even if companies like CXMT can expand their fabs faster, that additional capacity will mostly be consumed by domestic needs, according to Citrini.

It should be noted that to make more memory, DRAM makers need more fab tools, primarily 193nm immersion scanners. Yet, companies like ASML, Canon, and Nikon cannot increase output of immersion DUV systems quickly as these are extremely complex machines containing tens of thousands of parts. While Chinese memory companies certainly pin their hopes on local producers like SMEE and SiCarrier, neither has delivered a single commercial immersion system, and after they do, it will take them years to ramp up production of such tools.

SK Hynix CEO Kwak Noh-jung says that 2027 will be the "worst year" for the ongoing memory shortage in comments shared with Reuters. The remark comes on the heels of SK Hynix successfully marking the largest-ever IPO for a foreign company on the U.S. stock market, raising $26.5 billion. Although Kwak points to next year being the worst for RAM shortages, the executive expects the memory crunch to last until 2030.

"We forecast that next year will be the worst year in the industry's history from the supply perspective," Kwan told Reuters. "We still forecast that customer demand will remain higher than our ​supply capacity even beyond 2030. But we are doing our best to solve the problem."

In March, SK Group chairman Chey Tae-won also suggested shortages would last until 2030, and the company has previously pointed to 2027 as a key shortage point, alongside Samsung. DRAM demand is largely driven by the HBM used in AI accelerators, which require far more sophisticated manufacturing and packaging processes compared to consumer DDR5. On top of advanced manufacturing, HBM also consumes more wafer capacity than DDR5, forcing major memory brands to reallocate supply and double down on an already sticky supply situation.

Forecasts like this are tricky. It's in SK Hynix's financial interest for memory shortages to continue, even well beyond 2030. SK Hynix has set a record for quarter-over-quarter revenue, and rival Micron has seen its stock value increase 213% this year, pushing its share price to around $990.

However, Kwan's remarks aren't just a bid to rally behind SK Hynix stock. Over the past few months, we've seen Micron and SK Hynix ink long-term supply agreements (LTAs). These agreements commit supply over multiple years to particular companies and define a price floor and ceiling during the agreement term. Although LTAs don't directly influence market prices, they secure demand, and we've seen a lot of LTAs over the past several months to bind DRAM supply.

Although memory (and NAND) prices will remain elevated for at least the next several months, we've seen some signs of the market cooling. Earlier this month, a TrendForce report showed DRAM contract prices up 15% to 18% quarter over quarter for Q3 2026. That's a large increase, but far lower than the QoQ increases we've seen previously.

We're nearing some semblance of stability in the memory market, just stability at vastly elevated prices. How long that lasts is anyone's guess. Although memory brands like SK Hynix have visibility into market trends, those can rapidly change. Just this year, we've seen a massive pivot toward AI spending going toward CPUs, pushing Intel's stock to record highs while shedding around $1 trillion in Nvidia's market cap; a year ago, that would've been almost impossible to predict.

JEDEC has released its new specification that aims to push down the pricing of the ultra-expensive HBM that powers the fastest AI processors. While the new standard will not help relieve the DRAM shortage as it uses large HBM4 DRAM devices, it can make high-bandwidth memory a bit cheaper as it enables attaching SPHBM4 memory stacks without advanced packaging and using inexpensive organic substrates.

The standard's body published the specification of SPHBM4, Standard Package High Bandwidth Memory (JESD330-4), that combines HBM4 DRAM ICs with standard packaging and a fast 'narrow' 512-bit interface. Here are the details.

HBM4 performance with a 512-bit wide interface

Although 1024-bit and 2048-bit interfaces used by HBM3 and HBM4 memory deliver unbeatable performance, their wide interfaces consume significant silicon area inside processors, they require expensive interposers, and advanced packaging technologies with limited capacity, such as TSMC’s CoWoS, for integration with host processors. The upcoming SPHBM4 memory continues to use the same HBM4 DRAM stacks as JESD270-4, but swaps the conventional HBM base die for a new SPHBM4 PHY/buffer die featuring a narrower 512-bit interface that enables mounting on standard organic substrates without using sophisticated packaging methods for integration. To offset the effect of the narrower interface, SPHBM4 supports considerably higher data transfer rates ranging from 22.4 GT/s to 46.0 GT/s.

Instead of connecting to the host processor using a 2048-bit memory interface like HBM4, SPHBM4 uses 32 independent 16-bit DDR channels organized into eight Quad Channels. Since 'Quad Channel' is a new term, let us explain how things work. Internally, an HBM4 stack contains 32 memory channels, each 64 bits wide, for a total external interface width of 2048 bits. SPHBM4 needs to 'convert' the 2048-bit internal I/O onto a 512-bit external interface, which is why it groups every four HBM4 channels into a Quad Channel. As a result, externally, a Quad Channel exposes 64 data pins (4 × 16 bits), which replace the 256 data pins (4 × 64 bits) that those four HBM4 channels would normally require. To preserve bandwidth, these 64 pins operate at four times the data rate of the original HBM4 interface.

While SPHBM4 dramatically increases I/O bandwidth, it does not make the DRAM array itself faster. The HBM4 memory core retains the same fundamental architecture and timings, including core frequency, row activation, precharge, and refresh operations, though the additional PHY is expected to introduce some latency. For example, the DRAM core runs at only one-quarter of the external interface frequency, which means 2 GHz in the case of SPHBM4 with a 32 GT/s speed bin.

The major change is the new base die, which implements a high-speed SerDes-like PHY that maps each 16-bit external channel to four conventional 64-bit HBM4 channels. As a result, SPHBM4 introduces equalization, lane training, BER requirements, and other high-speed signaling features that are unnecessary in HBM4’s slower, wide parallel interface. To support transfer rates of up to 46.0 GT/s/s per pin, each Quad Channel uses a shared command/address interface protected by forward error correction (FEC), while data transfers rely on dedicated differential write (WCK) and read (RCK) clocks, as well as ECC and error-reporting signals.

When it comes to capacity, SPHBM4 can use stacks containing 4, 8, 12, or 16 DRAM dies featuring 24 Gb or 32 Gb densities, so the largest standardized SPHBM4 configuration is a 64 GB memory stack built from sixteen 32 Gb DRAM dies, identical to the maximum capacity supported by HBM4E.

Cheap HBM at last?

The standard supports bump pitches greater than 90 µm and channel reaches up to 20 mm, which are two features that enable dropping the expensive interposer and using less-expensive organic substrate routing. However, getting rid of the interposer and CoWoS (or similar) packaging does not automatically make SPHBM4 inexpensive. SPHBM4 still requires massive HBM4 DRAM ICs, 2.5D packaging, a complex base die (which is likely costlier than the one used by conventional HBM4), and advanced package assembly with through-silicon vias. In addition, SPHBM4's narrow interface consumes significantly less die perimeter and silicon area inside processors, which makes it more attractive to companies that strive to install more compute capability and/or intend to install more memory stacks around their processors. However, we are still talking about a niche high-performance memory technology that will address select applications and will barely rival HBM4 directly.

When it comes to maximum performance, HBM4 moves the data at 8 GT/s (though most controllers and chips support higher data rates), so one HBM4 stack can offer bandwidth of 2 TB/s. HBM4E is set to up data transfer rate to 12 – 12.8 GT/s, therefore increasing peak bandwidth to 3 – 3.3 TB/s per stack. By contrast, one SPHBM4 with a 46 GT/s interface can hit 2.944 TB/s, though do not expect the initial versions of SPHBM4 to hit the maximum speed. Therefore, it is likely that HBM4, HBM4E, and C-HBM4E will maintain a performance lead in terms of bandwidth over SPHBM4 in the foreseeable future.

HBM4 latency will still probably have an edge over SPHBM4. HBM4 essentially connects to its host processor almost directly through a very simple interface. By contrast, SPHBM4 inserts a much more sophisticated PHY that performs serialization/deserialization, lane training, FEC handling, and other operations that can add a few nanoseconds of latency. This may not be a big problem for some applications, but inference benefits a lot from low latencies.

When it comes to power and voltages, HBM4 and SPHBM4 share the same DRAM core voltage because SPHBM4 reuses standard HBM4 DRAM stacks. However, I/O is different: HBM4 leaves the interface voltage up to memory vendors and allows implementations at 0.7V, 0.75V, 0.8V, or 0.9V, depending on the desired balance between power, speed, and signal integrity. By contrast, SPHBM4 standardizes the external I/O at 0.75V.

Also, HBM4 moves data over a very wide interface with many slow parallel links that tend to be very energy efficient. By contrast, SPHBM4 moves the same amount of data through one-quarter as many wires, which run roughly four times faster. High-speed data transfer tends to be less energy efficient than 'slow' data transfers over a wide interface. Keeping in mind SPHBM4's rather sophisticated PHY that converts a wide interface into a narrow interface, which is likely a power-hungry process. Nonetheless, the 4X lower number of drivers and receivers could tangibly reduce the power consumption of SPHBM4. That said, without implementation details from DRAM makers or a processor developer, it is impossible to conclude which memory type has lower power consumption.

Last but not least, SPHBM4 essentially trades manufacturing challenges that arise from using silicon interposers for an engineering challenge of developing an extremely sophisticated base die/PHY. Developing and manufacturing such a base die should not be a problem for foundries. However, it remains to be seen whether DRAM makers can design and produce SPHBM4 with decent power efficiency. After all, both Micron and SK hynix work with TSMC to build C-HBM4E and HBM4E base dies, whereas Samsung's memory division uses base dies produced by Samsung Foundry.

China factor

One interesting aspect of SPHBM4 is whether Chinese developers of AI accelerators can benefit from this technology. In theory, Chinese developers like Biren, Huawei, Moore Threads, and other blacklisted companies that cannot use TSMC's chip manufacturing or packaging services could become one of the biggest beneficiaries of SPHBM4, perhaps even more so than the U.S.

First up, a smaller shoreline directly benefits chips that are made using trailing nodes, as it enables packing more compute capability into them without sacrificing memory bandwidth or capacity. Secondly, Chinese OSATs currently do not offer CoWoS-like technologies, so eliminating the interposer and using advanced organic substrates is a benefit.

However, SPHBM4 still requires HBM4 DRAM stacks, and today, Samsung, SK hynix, and Micron are the only companies capable of producing them, while China-based CXMT can barely make HBM2E. Furthermore, building a 46 GT/s PHY is very hard and will likely be challenging for Chinese IC developers.

Nonetheless, assembling SPHBM4 packages on organic substrates is arguably more aligned with China's existing manufacturing base, so if local DRAM makers eventually develop competitive HBM4-class memory, SPHBM4 could substantially reduce one of the country's remaining infrastructure gaps.

Summary

JEDEC's SPHBM4 looks like a promising standard that can potentially address a broader range of applications than HBM4 itself due to lower integration cost. Still, HBM4, HBM4E, and C-HBM4E will maintain performance leadership, which will make them a preferable choice for flagship AI accelerators in the coming years.

ChangXin Memory Technologies, or CXMT, has just received official validation from MSI for its high-speed DDR5 memory modules. The manufacturer has released new beta BIOSes across its AM5 lineup, unlocking stable frequencies up to 8,200 MT/s for 3GB CXMT chips on dual-DIMM motherboards. Previously, RAM using these modules was limited to around 6,800 MT/s despite the hardware itself being capable of much more.

The test BIOS comes from MSI China — there's no announcement on global channels for some reason, and it's only available for select motherboards at the moment. MSI tested region-bound retail kits from Lexar and KingBank on boards with both two slots and four slots, but we only have screenshots for the former, courtesy of Videocardz.

One test was conducted using 24GB sticks (2x24) on the MEG X870E Unify model and a Ryzen 7 9700X CPU. This was mostly a standard kit since it came with a 6,000 MT/s EXPO profile. The other config consisted of 16GB sticks (2x16) with an EXPO profile already running at 7,200 MT/s, so it was somewhat cherry-picked silicon, paired with a Ryzen 5 9600X on a MAG B850 MPower motherboard.

The results showed that on dual-DIMM motherboards, 24Gbit (3GB) modules from CXMT were able to clock up to 8,200 MT/s, passing MemTest with 101% coverage. Conversely, 16Gbit (2GB) chips were also stable at 8,000 MT/s on the same test bench with 101% coverage. Moving over to quad-DIMM, the patch notes for the BIOS say they've "also been raised to DDR5-7200," where the limit was stuck at 6,800 MT/s prior.

This is not the first time MSI has optimized Chinese RAM for some of its motherboards. Earlier this year, the company did the same thing for Intel's 800-series models in China. Anyway, these specific BIOSes are meant for the AM5 socket and they're based on existing stable releases — just patched with unlocked memory overclocking features. More motherboards should be supported soon, but for now you can check out the MSI China's community release channel if you want to try one yourself.

17 plaintiffs sued Samsung, SK hynix, and Micron in the U.S. District Court for the Northern District of California in late June, alleging the three companies, which together control roughly 90% of the global DRAM market, coordinated supply restrictions that pushed memory prices up around 700% in four years. The complaint is the third major legal assault on the DRAM industry in two decades. The first ended in criminal guilty pleas, roughly $730 million in fines, and prison terms for executives. The second collapsed in 2020; this new case must clear the same legal barrier that killed it.

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A cartel conviction, then a failed sequel

Between 1998 and 2002, DRAM makers fixed the price of memory sold to Dell, HP, Compaq, IBM, Gateway, and Apple, leading to a landmark case that saw the Department of Justice extract guilty pleas across the sector: $300 million from Samsung in 2005, then the second-largest criminal antitrust fine in U.S. history, alongside $185 million from Hynix, $160 million from Infineon, and $84 million from Elpida. More than a dozen execs served prison time in the U.S., while Micron, which admitted participating, escaped prosecution entirely by turning first under the DoJ's corporate leniency program.

Then, in 2018, Hagens Berman filed a class action alleging the same three companies colluded during the 2016-2017 upcycle, when DRAM prices roughly doubled and all three throttled supply growth in lockstep. The district court dismissed it in 2020, and the Ninth Circuit affirmed that decision in 2022, ruling the alleged conduct was “more likely explained by lawful, unchoreographed free-market behavior” than by agreement. The plaintiffs never reached the discovery phase in that case; it instead died on the pleadings, which is where this latest case is also likely to be decided.

Parallel conduct is legal

Section 1 of the Sherman Act punishes agreements in restraint of trade, but not identical behavior. When three firms in a concentrated market watch each other's earnings calls and rationally match each other’s output cuts, antitrust law calls it conscious parallelism and permits it.

Since the Supreme Court’s 2007 Twombly decision, a price-fixing complaint can overcome a motion to dismiss only if its factual allegations make an actual agreement plausible, not merely possible, and parallel conduct alone can never reach that threshold. Instead, plaintiffs need what are known as “plus factors”: actions against each firm's independent self-interest, suspicious communications, or opportunities to conspire that produce otherwise inexplicable behavior.

In the 2018 case, the plaintiffs offered eight plus factors, including trade-press statements about supply discipline and attendance at the same industry events, and both courts found them consistent with each company independently deciding that flooding a recovering market would be stupid. An oligopolist declining to start a price war isn’t evidence of a cartel; it’s evidence of an oligopoly.

2026's HBM pivot

What’s new in this case is that the complaint alleges the three memory makers used their pivot to high-bandwidth memory as a coordinated pretext to gut commodity DRAM output, curtailing DDR3 and DDR4 production far beyond what HBM demand required and starving the market that feeds PCs, phones, and servers.

The filing stacks supporting plus factors on top, including near-simultaneous production cuts announced in late 2022, Micron's decision last year to shut down its consumer-facing Crucial memory business and remove a retail supply channel, and the makers' synchronized customer-vetting regime introduced to block hoarding and resale, which the plaintiffs read as jointly policing who gets supply. Apple’s memory-driven iPad and Mac price increases appear in the complaint as downstream proof of harm.

HBM carries far higher margins than commodity DRAM, and every maker had an independent incentive to chase Nvidia’s order book. The late-2022 cuts came during the worst memory downturn in over a decade, when SK hynix and Micron were posting operating losses, and Samsung held out on cuts months longer than its rivals, which is awkward material for a case looking to rely on a lockstep narrative. Crucial's shutdown also coincided with Micron reallocating output toward data center customers paying more. As such, every allegation in the complaint has a non-conspiratorial explanation available, and under Twombly, the plaintiffs need there to be at least a plausible conspiracy theory to have a chance of success.

Motions to dismiss likely

A leading-edge DRAM fab costs $15 billion to $20 billion and takes years to bring up, so no fourth player can arbitrage the shortage away on any timescale that’s relevant to this case. Three firms facing inelastic demand and no threat of entry can sustain supracompetitive prices through nothing more than mutual self-restraint, and current numbers show what that looks like.

SK hynix reported a record operating margin above 70% in its most recent quarter, and the investment firm Jefferies expects DRAM contract prices to rise another 40% to 50% in the third quarter and 30% to 40% in the fourth, with no meaningful relief before 2028. SK Group chairman Chey Tae-won has put the end of the shortage even further out. Margins that fat are indeed consistent with a cartel, but they’re equally consistent with a demand shock hitting a market built to under-supply, and courts have declined to let juries choose between the two unless a seriously high evidential threshold has been reached. Here, that doesn’t appear to have happened. In addition, China’s CXMT is rapidly expanding DDR5 output with state backing, and any sustained market share gains and price pressure from it would undercut the complaint's premise that the incumbent big three face(d) no competitive pressure.

The defendants haven’t yet responded in court and are likely to file motions to dismiss. Surviving dismissal would force three companies, which are enjoying the most profitable memory cycle in history, to open their internal communications regarding HBM allocation and commodity wind-downs to plaintiffs’ lawyers for the first time. If the court follows the Ninth Circuit's 2022 reasoning instead, the suit joins its predecessor, and 90% of the world's DRAM supply continues to be governed by three firms whose parallel restraint, in the law’s eyes, remains just good business.

SK hynix this week announced that it would invest an additional KRW 100 trillion ($64 billion) in its Cheongju campus to expand production of 3D NAND and HBM packaging at the site. Given the vast investment, expect the company to add some massive production capacity, but unfortunately that production capacity is going to kick in only several years down the road. But that investment pales in front of the company's plan to invest $712.5 billion in its South Korean operations.

The massive KRW 100 trillion ($64 billion) in its Cheongju campus investment is only a part of SK hynix's grand plan to invest KRW 1.1 trillion ($712.5 billion) in a variety of projects in South Korea. In particular, the company intends to invest KRW 400 trillion ($259.5 billion) in its all-new Southwestern semiconductor cluster as well as KRW 600 trillion ($389.3 billion) in its Yongin site. While the Cheongju investment is considerably lower than investments in other campuses, it is the only project that is actually detailed enough.

$64 billion go to Cheongju to support NAND and packaging

SK hynix claims that it intends to build a 3D NAND fab, install manufacturing equipment, and expand its advanced packaging capabilities for HBM back-end processing at its Cheongju campus in the Chungcheong region. The company intends to start building its M17 fab next year, so the earliest timeframe it comes online is sometimes in 2029 at the earliest. The fab will cost around KRW 80 trillion ($51.8 billion), whereas the new P&T7 packaging and test facility will cost KRW 20 trillion ($12.945 billion).

SK hynix's campus in Cheongju houses some of the company's primary fabs that manufacture 3D NAND flash, including M11, M12, and M15, and historically it was the company's main 3D NAND memory manufacturing center. However, because multi-layer 3D NAND and high-bandwidth memory (HBM) stacks use similar packaging technologies, it is now evolving into a site that also makes HBM stacks: M15X produces actual DRAM dies, whereas P&T3 performs packaging operations.

But the investment in SK hynix's Cheongju NAND and HBM assembly operations pales when compared to how much money the company plans to pour into other projects.

$389.3 billion go to Yongin Semiconductor Cluster to boost DRAM output

SK hynix plans to invest approximately $389.3 billion in the Yongin Semiconductor Cluster, which is the company's largest investment commitment ever and which will make the campus its largest DRAM production site. Meanwhile, Yongin is a greenfield site today.

The first fab in Yongin is expected to commence operations in May 2027, while the remaining fabs will be added sequentially. It takes about a year or 1.5 years or so to fully ramp a DRAM fab, so expect the facility to impact the memory market in 2028 – 2029. Under the company's newly announced plan, construction of all four fabs is now targeted to complete the fourth fab by 2033, instead of the original 2045 timeline. The $389.3 billion investment extends beyond 2033.

$259.5 billion go to Southwestern Semiconductor Cluster

Unlike Yongin, the Southwestern Semiconductor Cluster does not even exist. It is currently a planned project, and SK hynix has not even selected a specific site within southwestern Korea. The company says the exact location will be determined after evaluating land availability, electricity, water, transportation, and other infrastructure requirements in consultation with central and local governments.

The cluster is envisioned as SK hynix's next major manufacturing base after Icheon, Cheongju, and Yongin. For now, the planned investment totals approximately $259.5 billion, though given that the project's completion is decades away, we can expect that number to change upwards or downwards depending on the market conditions and the cost of wafer fabrication equipment.

The investment will be phased over many years and cover land acquisition, fab construction, and production tools. SK hynix says preparations must begin now because developing a new semiconductor cluster — including site selection and infrastructure — takes many years. For example, development of the Yongin Cluster took about nine years, according to SK hynix.

Not alone

SK hynix is not alone in investing in South Korea. Samsung on Thursday announced plans to spend some KRW 140 trillion ($90.98 billion) in its operations in South Korea’s Chungcheong region.

Under the plan, Samsung Display will expand OLED production in Asan; Samsung Electronics will build five HBM production lines in Onyang and modernize HBM-related facilities in Cheonan; Samsung SDI will establish a battery production line in Cheonan to validate next-generation technologies before deploying them globally; and Samsung Electro-Mechanics will expand AI server package substrate manufacturing in Sejong.

The price of DDR5 memory is setting new highs these days as demand badly outstrips supply. In a bid to save money, Meta is recovering legacy DDR4 memory from used servers and is installing it into new machines using its in-house developed Vistara ASIC that enables it to connect old memory modules to its latest servers running AMD EPYC 'Turin' processors that only support DDR5 memory.

Interestingly, Meta is not the only company developing such a solution. Panmnesia, a startup from South Korea, has developed an off-the-shelf CXL controller and switch that enables servers to attach considerably larger memory pools without extending latency, which differentiates Panmnesia’s solution from competing CXL offerings.

Custom ASIC enables DDR4 memory to work with new servers

Vistara is Meta’s first-gen custom CXL memory expander ASIC designed to attach outdated DDR4 memory to modern servers. The chip implements a CXL 2.0 Type-3 memory expander over a PCIe 5.0 x16 interface and bridges standard DDR4 RDIMMs to host processors. Each ASIC supports two independent 72-bit DDR4 memory channels and can provide up to 256 GB of capacity using 64 GB DIMMs. At present, Meta deploys 128 GB per ASIC using 32 GB DDR4 modules recovered from decommissioned servers.

Meta deploys Vistara in its MemServer platform, where two ASICs connect to a single 158-core AMD Turin processor over PCIe 5.0 x8 links. Each server combines 768 GB of DDR5-6400 local memory with 256 GB of CXL-attached DDR4-2400, which expands memory capacity to 1 TB. The software stack transparently exposes CXL memory as a separate NUMA node and enables Linux to migrate cold pages to the slower DDR4 tier (with 76 GB/s of bandwidth) and retain frequently accessed data in local DDR5 (with 614 GB/s of bandwidth).

The ASIC is based on three RISC-V processor cores for secure boot, device initialization, firmware management, and health monitoring. Meta claims it has optimized its CXL controller and memory pipeline to reduce protocol overhead, minimize queuing delays, and lower idle round-trip latency to around 50ns. The chip also incorporates advanced reliability features, including Reed-Solomon two-symbol error correction and x4 chip-kill support.

Not only Meta's Vistara

Meta is not the only company that wants to attach legacy DDR4 memory to newer servers that rely on DDR5 memory and save some money. While Vistara is available exclusively to Meta, there is a new CXL expander solution from Panmnesia that will be available to other companies.

"There has been a perception that putting a switch between the CPU and devices makes it hard to meet the memory-access latency these systems expect, so directly attached multi-headed devices (MHDs) stayed the norm even though they were harder to scale," said Myoungsoo Jung, chief executive of Panmnesia. "Our work shows this is not an inherent limit of CXL or CXL switches — it is a trait of early-stage CXL, and one that fades as the standard and the products around it mature. With a fabric switch that carries our next-stage CXL controller, scalability, low latency, and stable performance can come together."

CXL is a protocol that sits on top of the PCIe physical interface. As a result of this, many early CXL implementations were built by modifying existing PCIe IP, which is why such implementations inherited architectural characteristics optimized for PCIe rather than for memory-semantic communications, which added substantial latency, according to Panmnesia. By contrast, its new CXL controller IP features a redesigned data path that replaces separate per-layer buffers with shared buffers to eliminate much of the synchronization overhead. In addition, it features additional latency optimizations throughout the protocol stack that offset the additional hop introduced by the switch.

The accompanying CXL fabric switch introduces Port-Based Routing (PBR), which removes the tree-topology limitations of conventional Hierarchy-Based Routing (HBR) used by PCIe and early CXL implementations. The fabric switch still supports both PBR and HBR to enable flexible system topologies, optimized traffic routing, and stable performance. In practice, it enables companies like Meta to install more DDR4 memory into their modern servers without major performance degradation because of high latency.

Panmnesia claims that while early CXL deployments could connect only a handful of compute nodes to shared memory pools, its fabric scales to up to 64 nodes, which means greater flexibility for hyperscalers that tend to run thousands of servers, but which now have to rationalize usage of expensive DRAM.

Panmnesia says its next-generation CXL technologies are progressing toward commercialization. The company has pre-release silicon for its PCIe 6.4/CXL 3.2 Fusion Switch and has completed development of its PCIe 7.0/CXL 4.0 Combo IP, which supports the latest features introduced by the CXL 4.0 specification.

In a world where memory is no longer a commodity but a strategically valuable asset, customers are eager to sign long-term supply agreements (LTAs) with their suppliers to ensure a steady supply of 3D NAND and/or DRAM. Micron this week announced that it had signed 16 strategic customer agreements (SCAs), 14 of which are worth around $100 billion. Furthermore, the company expects to receive cash deposits and other commitments worth $22 billion, but has warned there is no foreseeable end in sight to the RAM crisis driving up PC component prices.

“14 of the 16 SCAs that we have signed have a cumulative revenue at minimum price per our contracts of approximately $100 billion over the remaining agreement term,” a statement by Micron reads. “Under the SCAs we have signed so far, we project to receive cash deposits and related financial commitments of $22 billion.”

Based on Micron’s claims, the company has about $100 billion of guaranteed baseline revenue already locked in under 14 of those 16 strategic customer agreements, assuming customers only buy the minimum committed volumes and only pay the minimum contract price. In reality, Micron can earn more if customers buy higher volumes or pay higher prices. Furthermore, Micron expects customers who signed these long-term SCAs to put up real money up front — or make equivalent binding financial commitments — as part of reserving future memory supply.

Micron claims it has signed strategic customer agreements with four 'very large customers' and three 'medium-sized customers,' which means that the contracts were inked with clients that previously did not commit to LTAs. The contracts are signed with a five-year term (except the automotive LTAs, which have a term of three years), from calendar 2026 to calendar 2030.

Micron claims that memory supply will be insufficient in 2027 and may improve gradually only in 2028. To that end, it is not surprising that its clients are willing to sign LTAs for 3D NAND and DRAM to ensure that they have enough memory for their products.

"With respect to supply, our customers are recognizing that supply shortages in memory and storage will take considerable time to improve," said Sanjay Mehrotra, chief executive of Micron, in prepared remarks. "Even as we expect industry supply to improve gradually in 2028, we currently do not have line of sight as to when memory supply will be able to catch up with increasing demand."

Normally, Micron and other memory producers inked LTAs with select clients only (read: with Apple, Nvidia). 16 LTAs is a lot for this kind of arrangement, and this looks like a business model shift for the company. It is noteworthy that the 16 signed contracts represent roughly 20% of Micron's DRAM volume and 33% of the company's NAND volume over the period through 2030. That said, Micron may sign more LTAs with more companies.

DDR2 contract prices rose 55% to 60% in the second quarter of the year and are projected to climb another 35% to 40% in the third, according to research published this week by TrendForce, pushing the AI-driven memory shortage onto a standard that first shipped in 2003 and that the three largest DRAM makers stopped prioritizing years ago. The increases come from buyers redesigning products around older memory to secure supply, and from a split among the handful of remaining DDR2 suppliers, with Winbond reducing output as ESMT expands it.

The shortage hasn’t hit DDR2 directly, but Samsung, SK hynix, and Micron have steered wafer capacity toward HBM and server DRAM to feed AI infrastructure spending, thinning the supply of mature-node parts, including DDR4. As DDR4 tightened, OEMs and ODMs began specifying DDR3 in its place, and some DDR3 designs were reworked to use DDR2, with each tier of buyers chasing whatever generation it could still source. The result of this is shortages moving down through successive generations, something we saw unfolding back in March, when earlier data showed DDR3 and DDR2 prices rising 20% to 40% in a single month.

This continues the market inversion we’ve watched unfold throughout the year, as DDR4 climbed past DDR5 on price despite being slower and older, and in which module makers and motherboard vendors restarted DDR4 production after the big three had moved to wind it down.

Winbond and ESMT are the two main remaining sources of DDR2 components, and they’re responding to the squeeze in different ways. Winbond is gradually cutting DDR2 production to shift capacity toward higher-margin DDR3, DDR4, and LPDDR4, while ESMT is doing the reverse, concentrating its wafer allocation at foundry partner PSMC on DDR2 to capture the demand Winbond is tossing aside. Taiwanese suppliers, including Nanya, are already struggling to match the volume of orders migrating down from DDR4, and because new capacity depends on slow process migration, Winbond's withdrawal removes supply faster than ESMT can replace it.

Of course, today’s PCs don’t use DDR2, so we’re likely to see the impact of these price increases landing in areas like embedded systems, networking equipment, industrial controllers, automotive electronics, and other long-lived devices that were designed around it and are too costly to requalify on newer memory generations like DDR4 and five.

The spread of rising contract prices to DDR2 suggests that we’re staring down the barrel of a very long-term DRAM shortage. Contract prices across the wider market are still rising with no sign of levelling off, and meaningful new capacity isn’t expected until late 2027 at the earliest as a best-case scenario.